2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
52 interrupt-parent = <&intc>;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
110 #address-cells = <1>;
114 compatible = "arm,cortex-a8";
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
125 #cooling-cells = <2>;
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 cpu_alert0: cpu-alert0 {
146 temperature = <850000>;
153 temperature = <100000>;
162 #address-cells = <1>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-output-names = "osc24M";
175 compatible = "fixed-clock";
176 clock-frequency = <32768>;
177 clock-output-names = "osc32k";
182 compatible = "allwinner,sun4i-a10-display-engine";
183 allwinner,pipelines = <&fe0>, <&fe1>;
188 compatible = "simple-bus";
189 #address-cells = <1>;
193 sram-controller@1c00000 {
194 compatible = "allwinner,sun4i-a10-sram-controller";
195 reg = <0x01c00000 0x30>;
196 #address-cells = <1>;
201 compatible = "mmio-sram";
202 reg = <0x00000000 0xc000>;
203 #address-cells = <1>;
205 ranges = <0 0x00000000 0xc000>;
207 emac_sram: sram-section@8000 {
208 compatible = "allwinner,sun4i-a10-sram-a3-a4";
209 reg = <0x8000 0x4000>;
215 compatible = "mmio-sram";
216 reg = <0x00010000 0x1000>;
217 #address-cells = <1>;
219 ranges = <0 0x00010000 0x1000>;
221 otg_sram: sram-section@0 {
222 compatible = "allwinner,sun4i-a10-sram-d";
223 reg = <0x0000 0x1000>;
229 dma: dma-controller@1c02000 {
230 compatible = "allwinner,sun4i-a10-dma";
231 reg = <0x01c02000 0x1000>;
233 clocks = <&ccu CLK_AHB_DMA>;
238 compatible = "allwinner,sun4i-a10-nand";
239 reg = <0x01c03000 0x1000>;
241 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
242 clock-names = "ahb", "mod";
243 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
246 #address-cells = <1>;
251 compatible = "allwinner,sun4i-a10-spi";
252 reg = <0x01c05000 0x1000>;
254 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
255 clock-names = "ahb", "mod";
256 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
257 <&dma SUN4I_DMA_DEDICATED 26>;
258 dma-names = "rx", "tx";
260 #address-cells = <1>;
265 compatible = "allwinner,sun4i-a10-spi";
266 reg = <0x01c06000 0x1000>;
268 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
269 clock-names = "ahb", "mod";
270 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
271 <&dma SUN4I_DMA_DEDICATED 8>;
272 dma-names = "rx", "tx";
273 pinctrl-names = "default";
274 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
276 #address-cells = <1>;
280 emac: ethernet@1c0b000 {
281 compatible = "allwinner,sun4i-a10-emac";
282 reg = <0x01c0b000 0x1000>;
284 clocks = <&ccu CLK_AHB_EMAC>;
285 allwinner,sram = <&emac_sram 1>;
286 pinctrl-names = "default";
287 pinctrl-0 = <&emac_pins>;
292 compatible = "allwinner,sun4i-a10-mdio";
293 reg = <0x01c0b080 0x14>;
295 #address-cells = <1>;
299 tcon0: lcd-controller@1c0c000 {
300 compatible = "allwinner,sun4i-a10-tcon";
301 reg = <0x01c0c000 0x1000>;
303 resets = <&ccu RST_TCON0>;
305 clocks = <&ccu CLK_AHB_LCD0>,
306 <&ccu CLK_TCON0_CH0>,
307 <&ccu CLK_TCON0_CH1>;
311 clock-output-names = "tcon0-pixel-clock";
312 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
315 #address-cells = <1>;
319 #address-cells = <1>;
323 tcon0_in_be0: endpoint@0 {
325 remote-endpoint = <&be0_out_tcon0>;
328 tcon0_in_be1: endpoint@1 {
330 remote-endpoint = <&be1_out_tcon0>;
335 #address-cells = <1>;
339 tcon0_out_hdmi: endpoint@1 {
341 remote-endpoint = <&hdmi_in_tcon0>;
342 allwinner,tcon-channel = <1>;
348 tcon1: lcd-controller@1c0d000 {
349 compatible = "allwinner,sun4i-a10-tcon";
350 reg = <0x01c0d000 0x1000>;
352 resets = <&ccu RST_TCON1>;
354 clocks = <&ccu CLK_AHB_LCD1>,
355 <&ccu CLK_TCON1_CH0>,
356 <&ccu CLK_TCON1_CH1>;
360 clock-output-names = "tcon1-pixel-clock";
361 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
364 #address-cells = <1>;
368 #address-cells = <1>;
372 tcon1_in_be0: endpoint@0 {
374 remote-endpoint = <&be0_out_tcon1>;
377 tcon1_in_be1: endpoint@1 {
379 remote-endpoint = <&be1_out_tcon1>;
384 #address-cells = <1>;
388 tcon1_out_hdmi: endpoint@1 {
390 remote-endpoint = <&hdmi_in_tcon1>;
391 allwinner,tcon-channel = <1>;
398 compatible = "allwinner,sun4i-a10-mmc";
399 reg = <0x01c0f000 0x1000>;
400 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
401 clock-names = "ahb", "mmc";
403 pinctrl-names = "default";
404 pinctrl-0 = <&mmc0_pins>;
406 #address-cells = <1>;
411 compatible = "allwinner,sun4i-a10-mmc";
412 reg = <0x01c10000 0x1000>;
413 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
414 clock-names = "ahb", "mmc";
417 #address-cells = <1>;
422 compatible = "allwinner,sun4i-a10-mmc";
423 reg = <0x01c11000 0x1000>;
424 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
425 clock-names = "ahb", "mmc";
428 #address-cells = <1>;
433 compatible = "allwinner,sun4i-a10-mmc";
434 reg = <0x01c12000 0x1000>;
435 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
436 clock-names = "ahb", "mmc";
439 #address-cells = <1>;
443 usb_otg: usb@1c13000 {
444 compatible = "allwinner,sun4i-a10-musb";
445 reg = <0x01c13000 0x0400>;
446 clocks = <&ccu CLK_AHB_OTG>;
448 interrupt-names = "mc";
451 extcon = <&usbphy 0>;
452 allwinner,sram = <&otg_sram 1>;
456 usbphy: phy@1c13400 {
458 compatible = "allwinner,sun4i-a10-usb-phy";
459 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
460 reg-names = "phy_ctrl", "pmu1", "pmu2";
461 clocks = <&ccu CLK_USB_PHY>;
462 clock-names = "usb_phy";
463 resets = <&ccu RST_USB_PHY0>,
466 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
471 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
472 reg = <0x01c14000 0x100>;
474 clocks = <&ccu CLK_AHB_EHCI0>;
481 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
482 reg = <0x01c14400 0x100>;
484 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
490 crypto: crypto-engine@1c15000 {
491 compatible = "allwinner,sun4i-a10-crypto";
492 reg = <0x01c15000 0x1000>;
494 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
495 clock-names = "ahb", "mod";
499 compatible = "allwinner,sun4i-a10-hdmi";
500 reg = <0x01c16000 0x1000>;
502 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
503 <&ccu CLK_PLL_VIDEO0_2X>,
504 <&ccu CLK_PLL_VIDEO1_2X>;
505 clock-names = "ahb", "mod", "pll-0", "pll-1";
506 dmas = <&dma SUN4I_DMA_NORMAL 16>,
507 <&dma SUN4I_DMA_NORMAL 16>,
508 <&dma SUN4I_DMA_DEDICATED 24>;
509 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
513 #address-cells = <1>;
517 #address-cells = <1>;
521 hdmi_in_tcon0: endpoint@0 {
523 remote-endpoint = <&tcon0_out_hdmi>;
526 hdmi_in_tcon1: endpoint@1 {
528 remote-endpoint = <&tcon1_out_hdmi>;
533 #address-cells = <1>;
541 compatible = "allwinner,sun4i-a10-spi";
542 reg = <0x01c17000 0x1000>;
544 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
545 clock-names = "ahb", "mod";
546 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
547 <&dma SUN4I_DMA_DEDICATED 28>;
548 dma-names = "rx", "tx";
550 #address-cells = <1>;
555 compatible = "allwinner,sun4i-a10-ahci";
556 reg = <0x01c18000 0x1000>;
558 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
563 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
564 reg = <0x01c1c000 0x100>;
566 clocks = <&ccu CLK_AHB_EHCI1>;
573 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
574 reg = <0x01c1c400 0x100>;
576 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
583 compatible = "allwinner,sun4i-a10-spi";
584 reg = <0x01c1f000 0x1000>;
586 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
587 clock-names = "ahb", "mod";
588 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
589 <&dma SUN4I_DMA_DEDICATED 30>;
590 dma-names = "rx", "tx";
592 #address-cells = <1>;
597 compatible = "allwinner,sun4i-a10-ccu";
598 reg = <0x01c20000 0x400>;
599 clocks = <&osc24M>, <&osc32k>;
600 clock-names = "hosc", "losc";
605 intc: interrupt-controller@1c20400 {
606 compatible = "allwinner,sun4i-a10-ic";
607 reg = <0x01c20400 0x400>;
608 interrupt-controller;
609 #interrupt-cells = <1>;
612 pio: pinctrl@1c20800 {
613 compatible = "allwinner,sun4i-a10-pinctrl";
614 reg = <0x01c20800 0x400>;
616 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
617 clock-names = "apb", "hosc", "losc";
619 interrupt-controller;
620 #interrupt-cells = <3>;
623 can0_ph_pins: can0-ph-pins {
624 pins = "PH20", "PH21";
628 emac_pins: emac0-pins {
629 pins = "PA0", "PA1", "PA2",
630 "PA3", "PA4", "PA5", "PA6",
631 "PA7", "PA8", "PA9", "PA10",
632 "PA11", "PA12", "PA13", "PA14",
637 i2c0_pins: i2c0-pins {
642 i2c1_pins: i2c1-pins {
643 pins = "PB18", "PB19";
647 i2c2_pins: i2c2-pins {
648 pins = "PB20", "PB21";
652 ir0_rx_pins: ir0-rx-pin {
657 ir0_tx_pins: ir0-tx-pin {
662 ir1_rx_pins: ir1-rx-pin {
667 ir1_tx_pins: ir1-tx-pin {
672 mmc0_pins: mmc0-pins {
673 pins = "PF0", "PF1", "PF2",
676 drive-strength = <30>;
680 ps2_ch0_pins: ps2-ch0-pins {
681 pins = "PI20", "PI21";
685 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
686 pins = "PH12", "PH13";
700 spdif_tx_pin: spdif-tx-pin {
706 spi0_pi_pins: spi0-pi-pins {
707 pins = "PI11", "PI12", "PI13";
711 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
716 spi1_pins: spi1-pins {
717 pins = "PI17", "PI18", "PI19";
721 spi1_cs0_pin: spi1-cs0-pin {
726 spi2_pb_pins: spi2-pb-pins {
727 pins = "PB15", "PB16", "PB17";
731 spi2_pc_pins: spi2-pc-pins {
732 pins = "PC20", "PC21", "PC22";
736 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
741 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
746 uart0_pb_pins: uart0-pb-pins {
747 pins = "PB22", "PB23";
751 uart0_pf_pins: uart0-pf-pins {
756 uart1_pins: uart1-pins {
757 pins = "PA10", "PA11";
763 compatible = "allwinner,sun4i-a10-timer";
764 reg = <0x01c20c00 0x90>;
769 wdt: watchdog@1c20c90 {
770 compatible = "allwinner,sun4i-a10-wdt";
771 reg = <0x01c20c90 0x10>;
775 compatible = "allwinner,sun4i-a10-rtc";
776 reg = <0x01c20d00 0x20>;
781 compatible = "allwinner,sun4i-a10-pwm";
782 reg = <0x01c20e00 0xc>;
788 spdif: spdif@1c21000 {
789 #sound-dai-cells = <0>;
790 compatible = "allwinner,sun4i-a10-spdif";
791 reg = <0x01c21000 0x400>;
793 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
794 clock-names = "apb", "spdif";
795 dmas = <&dma SUN4I_DMA_NORMAL 2>,
796 <&dma SUN4I_DMA_NORMAL 2>;
797 dma-names = "rx", "tx";
802 compatible = "allwinner,sun4i-a10-ir";
803 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
804 clock-names = "apb", "ir";
806 reg = <0x01c21800 0x40>;
811 compatible = "allwinner,sun4i-a10-ir";
812 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
813 clock-names = "apb", "ir";
815 reg = <0x01c21c00 0x40>;
820 #sound-dai-cells = <0>;
821 compatible = "allwinner,sun4i-a10-i2s";
822 reg = <0x01c22400 0x400>;
824 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
825 clock-names = "apb", "mod";
826 dmas = <&dma SUN4I_DMA_NORMAL 3>,
827 <&dma SUN4I_DMA_NORMAL 3>;
828 dma-names = "rx", "tx";
832 lradc: lradc@1c22800 {
833 compatible = "allwinner,sun4i-a10-lradc-keys";
834 reg = <0x01c22800 0x100>;
839 codec: codec@1c22c00 {
840 #sound-dai-cells = <0>;
841 compatible = "allwinner,sun4i-a10-codec";
842 reg = <0x01c22c00 0x40>;
844 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
845 clock-names = "apb", "codec";
846 dmas = <&dma SUN4I_DMA_NORMAL 19>,
847 <&dma SUN4I_DMA_NORMAL 19>;
848 dma-names = "rx", "tx";
852 sid: eeprom@1c23800 {
853 compatible = "allwinner,sun4i-a10-sid";
854 reg = <0x01c23800 0x10>;
858 compatible = "allwinner,sun4i-a10-ts";
859 reg = <0x01c25000 0x100>;
861 #thermal-sensor-cells = <0>;
864 uart0: serial@1c28000 {
865 compatible = "snps,dw-apb-uart";
866 reg = <0x01c28000 0x400>;
870 clocks = <&ccu CLK_APB1_UART0>;
874 uart1: serial@1c28400 {
875 compatible = "snps,dw-apb-uart";
876 reg = <0x01c28400 0x400>;
880 clocks = <&ccu CLK_APB1_UART1>;
884 uart2: serial@1c28800 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0x01c28800 0x400>;
890 clocks = <&ccu CLK_APB1_UART2>;
894 uart3: serial@1c28c00 {
895 compatible = "snps,dw-apb-uart";
896 reg = <0x01c28c00 0x400>;
900 clocks = <&ccu CLK_APB1_UART3>;
904 uart4: serial@1c29000 {
905 compatible = "snps,dw-apb-uart";
906 reg = <0x01c29000 0x400>;
910 clocks = <&ccu CLK_APB1_UART4>;
914 uart5: serial@1c29400 {
915 compatible = "snps,dw-apb-uart";
916 reg = <0x01c29400 0x400>;
920 clocks = <&ccu CLK_APB1_UART5>;
924 uart6: serial@1c29800 {
925 compatible = "snps,dw-apb-uart";
926 reg = <0x01c29800 0x400>;
930 clocks = <&ccu CLK_APB1_UART6>;
934 uart7: serial@1c29c00 {
935 compatible = "snps,dw-apb-uart";
936 reg = <0x01c29c00 0x400>;
940 clocks = <&ccu CLK_APB1_UART7>;
945 compatible = "allwinner,sun4i-a10-ps2";
946 reg = <0x01c2a000 0x400>;
948 clocks = <&ccu CLK_APB1_PS20>;
953 compatible = "allwinner,sun4i-a10-ps2";
954 reg = <0x01c2a400 0x400>;
956 clocks = <&ccu CLK_APB1_PS21>;
961 compatible = "allwinner,sun4i-a10-i2c";
962 reg = <0x01c2ac00 0x400>;
964 clocks = <&ccu CLK_APB1_I2C0>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&i2c0_pins>;
968 #address-cells = <1>;
973 compatible = "allwinner,sun4i-a10-i2c";
974 reg = <0x01c2b000 0x400>;
976 clocks = <&ccu CLK_APB1_I2C1>;
977 pinctrl-names = "default";
978 pinctrl-0 = <&i2c1_pins>;
980 #address-cells = <1>;
985 compatible = "allwinner,sun4i-a10-i2c";
986 reg = <0x01c2b400 0x400>;
988 clocks = <&ccu CLK_APB1_I2C2>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&i2c2_pins>;
992 #address-cells = <1>;
997 compatible = "allwinner,sun4i-a10-can";
998 reg = <0x01c2bc00 0x400>;
1000 clocks = <&ccu CLK_APB1_CAN>;
1001 status = "disabled";
1004 fe0: display-frontend@1e00000 {
1005 compatible = "allwinner,sun4i-a10-display-frontend";
1006 reg = <0x01e00000 0x20000>;
1008 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1009 <&ccu CLK_DRAM_DE_FE0>;
1010 clock-names = "ahb", "mod",
1012 resets = <&ccu RST_DE_FE0>;
1015 #address-cells = <1>;
1019 #address-cells = <1>;
1023 fe0_out_be0: endpoint@0 {
1025 remote-endpoint = <&be0_in_fe0>;
1028 fe0_out_be1: endpoint@1 {
1030 remote-endpoint = <&be1_in_fe0>;
1036 fe1: display-frontend@1e20000 {
1037 compatible = "allwinner,sun4i-a10-display-frontend";
1038 reg = <0x01e20000 0x20000>;
1040 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1041 <&ccu CLK_DRAM_DE_FE1>;
1042 clock-names = "ahb", "mod",
1044 resets = <&ccu RST_DE_FE1>;
1047 #address-cells = <1>;
1051 #address-cells = <1>;
1055 fe1_out_be0: endpoint@0 {
1057 remote-endpoint = <&be0_in_fe1>;
1060 fe1_out_be1: endpoint@1 {
1062 remote-endpoint = <&be1_in_fe1>;
1068 be1: display-backend@1e40000 {
1069 compatible = "allwinner,sun4i-a10-display-backend";
1070 reg = <0x01e40000 0x10000>;
1072 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1073 <&ccu CLK_DRAM_DE_BE1>;
1074 clock-names = "ahb", "mod",
1076 resets = <&ccu RST_DE_BE1>;
1079 #address-cells = <1>;
1083 #address-cells = <1>;
1087 be1_in_fe0: endpoint@0 {
1089 remote-endpoint = <&fe0_out_be1>;
1092 be1_in_fe1: endpoint@1 {
1094 remote-endpoint = <&fe1_out_be1>;
1099 #address-cells = <1>;
1103 be1_out_tcon0: endpoint@0 {
1105 remote-endpoint = <&tcon0_in_be1>;
1108 be1_out_tcon1: endpoint@1 {
1110 remote-endpoint = <&tcon1_in_be1>;
1116 be0: display-backend@1e60000 {
1117 compatible = "allwinner,sun4i-a10-display-backend";
1118 reg = <0x01e60000 0x10000>;
1120 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1121 <&ccu CLK_DRAM_DE_BE0>;
1122 clock-names = "ahb", "mod",
1124 resets = <&ccu RST_DE_BE0>;
1127 #address-cells = <1>;
1131 #address-cells = <1>;
1135 be0_in_fe0: endpoint@0 {
1137 remote-endpoint = <&fe0_out_be0>;
1140 be0_in_fe1: endpoint@1 {
1142 remote-endpoint = <&fe1_out_be0>;
1147 #address-cells = <1>;
1151 be0_out_tcon0: endpoint@0 {
1153 remote-endpoint = <&tcon0_in_be0>;
1156 be0_out_tcon1: endpoint@1 {
1158 remote-endpoint = <&tcon1_in_be0>;