arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
   9 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
  10
  11 / {
  12         aliases {
  13                 i2c1 = &i2c2;
  14                 i2c3 = &i2c4;
  15                 i2c4 = &i2c5;
  16                 mmc0 = &sdmmc1;
  17                 mmc1 = &sdmmc2;
  18                 spi0 = &qspi;
  19                 usb0 = &usbotg_hs;
  20         };
  21
  22         config {
  23                 u-boot,boot-led = "heartbeat";
  24                 u-boot,error-led = "error";
  25                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  26                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  27                 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
  28                 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
  29         };
  30
  31         led {
  32                 red {
  33                         label = "error";
  34                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  35                         default-state = "off";
  36                         status = "okay";
  37                 };
  38
  39                 blue {
  40                         default-state = "on";
  41                 };
  42         };
  43
  44         /* This is actually on FMC2, but we do not have bus driver for that */
  45         ksz8851: ks8851mll@64000000 {
  46                 compatible = "micrel,ks8851-mll";
  47                 reg = <0x64000000 0x20000>;
  48         };
  49 };
  50
  51 &i2c4 {
  52         u-boot,dm-pre-reloc;
  53 };
  54
  55 &i2c4_pins_a {
  56         u-boot,dm-pre-reloc;
  57         pins {
  58                 u-boot,dm-pre-reloc;
  59         };
  60 };
  61
  62 &pinctrl {
  63         /* These should bound to FMC2 bus driver, but we do not have one */
  64         pinctrl-0 = <&fmc_pins_b>;
  65         pinctrl-1 = <&fmc_sleep_pins_b>;
  66         pinctrl-names = "default", "sleep";
  67
  68         fmc_pins_b: fmc-0 {
  69                 pins1 {
  70                         pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
  71                                  <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
  72                                  <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
  73                                  <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
  74                                  <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
  75                                  <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
  76                                  <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
  77                                  <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
  78                                  <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
  79                                  <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
  80                                  <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
  81                                  <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
  82                                  <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
  83                                  <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
  84                                  <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
  85                                  <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
  86                                  <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
  87                                  <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
  88                                  <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
  89                                  <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
  90                                  <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
  91                         bias-disable;
  92                         drive-push-pull;
  93                         slew-rate = <3>;
  94                 };
  95         };
  96
  97         fmc_sleep_pins_b: fmc-sleep-0 {
  98                 pins {
  99                         pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
 100                                  <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
 101                                  <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
 102                                  <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
 103                                  <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
 104                                  <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
 105                                  <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
 106                                  <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
 107                                  <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
 108                                  <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
 109                                  <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
 110                                  <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
 111                                  <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
 112                                  <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
 113                                  <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
 114                                  <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
 115                                  <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
 116                                  <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
 117                                  <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
 118                                  <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
 119                                  <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
 120                 };
 121         };
 122 };
 123
 124 &pmic {
 125         u-boot,dm-pre-reloc;
 126 };
 127
 128 &flash0 {
 129         u-boot,dm-spl;
 130 };
 131
 132 &qspi {
 133         u-boot,dm-spl;
 134 };
 135
 136 &qspi_clk_pins_a {
 137         u-boot,dm-spl;
 138         pins {
 139                 u-boot,dm-spl;
 140         };
 141 };
 142
 143 &qspi_bk1_pins_a {
 144         u-boot,dm-spl;
 145         pins1 {
 146                 u-boot,dm-spl;
 147         };
 148         pins2 {
 149                 u-boot,dm-spl;
 150         };
 151 };
 152
 153 &qspi_bk2_pins_a {
 154         u-boot,dm-spl;
 155         pins1 {
 156                 u-boot,dm-spl;
 157         };
 158         pins2 {
 159                 u-boot,dm-spl;
 160         };
 161 };
 162
 163 &rcc {
 164         st,clksrc = <
 165                 CLK_MPU_PLL1P
 166                 CLK_AXI_PLL2P
 167                 CLK_MCU_PLL3P
 168                 CLK_PLL12_HSE
 169                 CLK_PLL3_HSE
 170                 CLK_PLL4_HSE
 171                 CLK_RTC_LSE
 172                 CLK_MCO1_DISABLED
 173                 CLK_MCO2_DISABLED
 174         >;
 175
 176         st,clkdiv = <
 177                 1 /*MPU*/
 178                 0 /*AXI*/
 179                 0 /*MCU*/
 180                 1 /*APB1*/
 181                 1 /*APB2*/
 182                 1 /*APB3*/
 183                 1 /*APB4*/
 184                 2 /*APB5*/
 185                 23 /*RTC*/
 186                 0 /*MCO1*/
 187                 0 /*MCO2*/
 188         >;
 189
 190         st,pkcs = <
 191                 CLK_CKPER_HSE
 192                 CLK_FMC_ACLK
 193                 CLK_QSPI_ACLK
 194                 CLK_ETH_PLL4P
 195                 CLK_SDMMC12_PLL4P
 196                 CLK_DSI_DSIPLL
 197                 CLK_STGEN_HSE
 198                 CLK_USBPHY_HSE
 199                 CLK_SPI2S1_PLL3Q
 200                 CLK_SPI2S23_PLL3Q
 201                 CLK_SPI45_HSI
 202                 CLK_SPI6_HSI
 203                 CLK_I2C46_HSI
 204                 CLK_SDMMC3_PLL4P
 205                 CLK_USBO_USBPHY
 206                 CLK_ADC_CKPER
 207                 CLK_CEC_LSE
 208                 CLK_I2C12_HSI
 209                 CLK_I2C35_HSI
 210                 CLK_UART1_HSI
 211                 CLK_UART24_HSI
 212                 CLK_UART35_HSI
 213                 CLK_UART6_HSI
 214                 CLK_UART78_HSI
 215                 CLK_SPDIF_PLL4P
 216                 CLK_FDCAN_PLL4R
 217                 CLK_SAI1_PLL3Q
 218                 CLK_SAI2_PLL3Q
 219                 CLK_SAI3_PLL3Q
 220                 CLK_SAI4_PLL3Q
 221                 CLK_RNG1_LSI
 222                 CLK_RNG2_LSI
 223                 CLK_LPTIM1_PCLK1
 224                 CLK_LPTIM23_PCLK3
 225                 CLK_LPTIM45_LSE
 226         >;
 227
 228         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 229         pll1: st,pll@0 {
 230                 compatible = "st,stm32mp1-pll";
 231                 reg = <0>;
 232                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 233                 frac = < 0x800 >;
 234                 u-boot,dm-pre-reloc;
 235         };
 236
 237         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 238         pll2: st,pll@1 {
 239                 compatible = "st,stm32mp1-pll";
 240                 reg = <1>;
 241                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 242                 frac = < 0x1400 >;
 243                 u-boot,dm-pre-reloc;
 244         };
 245
 246         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 247         pll3: st,pll@2 {
 248                 compatible = "st,stm32mp1-pll";
 249                 reg = <2>;
 250                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 251                 frac = < 0x1a04 >;
 252                 u-boot,dm-pre-reloc;
 253         };
 254
 255         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 256         pll4: st,pll@3 {
 257                 compatible = "st,stm32mp1-pll";
 258                 reg = <3>;
 259                 cfg = < 1 49 11 11 11 PQR(1,1,1) >;
 260                 u-boot,dm-pre-reloc;
 261         };
 262 };
 263
 264 &sdmmc1 {
 265         u-boot,dm-spl;
 266 };
 267
 268 &sdmmc1_b4_pins_a {
 269         u-boot,dm-spl;
 270         pins1 {
 271                 u-boot,dm-spl;
 272         };
 273         pins2 {
 274                 u-boot,dm-spl;
 275         };
 276 };
 277
 278 &sdmmc1_dir_pins_a {
 279         u-boot,dm-spl;
 280         pins1 {
 281                 u-boot,dm-spl;
 282         };
 283         pins2 {
 284                 u-boot,dm-spl;
 285         };
 286 };
 287
 288 &sdmmc2 {
 289         u-boot,dm-spl;
 290 };
 291
 292 &sdmmc2_b4_pins_a {
 293         u-boot,dm-spl;
 294         pins {
 295                 u-boot,dm-spl;
 296         };
 297 };
 298
 299 &sdmmc2_d47_pins_a {
 300         u-boot,dm-spl;
 301         pins {
 302                 u-boot,dm-spl;
 303         };
 304 };
 305
 306 &uart4 {
 307         u-boot,dm-pre-reloc;
 308 };
 309
 310 &uart4_pins_a {
 311         u-boot,dm-pre-reloc;
 312         pins1 {
 313                 u-boot,dm-pre-reloc;
 314         };
 315         pins2 {
 316                 u-boot,dm-pre-reloc;
 317                 /* pull-up on rx to avoid floating level */
 318                 bias-pull-up;
 319         };
 320 };