arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp15-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c1 = &i2c2;
  13                 i2c3 = &i2c4;
  14                 i2c4 = &i2c5;
  15                 mmc0 = &sdmmc1;
  16                 mmc1 = &sdmmc2;
  17                 spi0 = &qspi;
  18                 usb0 = &usbotg_hs;
  19         };
  20
  21         config {
  22                 u-boot,boot-led = "heartbeat";
  23                 u-boot,error-led = "error";
  24                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  25                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  26         };
  27
  28         led {
  29                 red {
  30                         label = "error";
  31                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  32                         default-state = "off";
  33                         status = "okay";
  34                 };
  35
  36                 blue {
  37                         default-state = "on";
  38                 };
  39         };
  40
  41         /* This is actually on FMC2, but we do not have bus driver for that */
  42         ksz8851: ks8851mll@64000000 {
  43                 compatible = "micrel,ks8851-mll";
  44                 reg = <0x64000000 0x20000>;
  45         };
  46 };
  47
  48 &i2c4 {
  49         u-boot,dm-pre-reloc;
  50 };
  51
  52 &i2c4_pins_a {
  53         u-boot,dm-pre-reloc;
  54         pins {
  55                 u-boot,dm-pre-reloc;
  56         };
  57 };
  58
  59 &pinctrl {
  60         /* These should bound to FMC2 bus driver, but we do not have one */
  61         pinctrl-0 = <&fmc_pins_b>;
  62         pinctrl-1 = <&fmc_sleep_pins_b>;
  63         pinctrl-names = "default", "sleep";
  64
  65         fmc_pins_b: fmc-0 {
  66                 pins1 {
  67                         pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
  68                                  <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
  69                                  <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
  70                                  <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
  71                                  <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
  72                                  <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
  73                                  <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
  74                                  <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
  75                                  <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
  76                                  <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
  77                                  <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
  78                                  <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
  79                                  <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
  80                                  <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
  81                                  <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
  82                                  <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
  83                                  <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
  84                                  <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
  85                                  <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
  86                                  <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
  87                                  <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
  88                         bias-disable;
  89                         drive-push-pull;
  90                         slew-rate = <3>;
  91                 };
  92         };
  93
  94         fmc_sleep_pins_b: fmc-sleep-0 {
  95                 pins {
  96                         pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
  97                                  <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
  98                                  <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
  99                                  <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
 100                                  <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
 101                                  <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
 102                                  <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
 103                                  <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
 104                                  <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
 105                                  <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
 106                                  <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
 107                                  <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
 108                                  <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
 109                                  <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
 110                                  <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
 111                                  <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
 112                                  <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
 113                                  <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
 114                                  <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
 115                                  <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
 116                                  <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
 117                 };
 118         };
 119 };
 120
 121 &pmic {
 122         u-boot,dm-pre-reloc;
 123 };
 124
 125 &flash0 {
 126         u-boot,dm-spl;
 127 };
 128
 129 &qspi {
 130         u-boot,dm-spl;
 131 };
 132
 133 &qspi_clk_pins_a {
 134         u-boot,dm-spl;
 135         pins {
 136                 u-boot,dm-spl;
 137         };
 138 };
 139
 140 &qspi_bk1_pins_a {
 141         u-boot,dm-spl;
 142         pins1 {
 143                 u-boot,dm-spl;
 144         };
 145         pins2 {
 146                 u-boot,dm-spl;
 147         };
 148 };
 149
 150 &qspi_bk2_pins_a {
 151         u-boot,dm-spl;
 152         pins1 {
 153                 u-boot,dm-spl;
 154         };
 155         pins2 {
 156                 u-boot,dm-spl;
 157         };
 158 };
 159
 160 &rcc {
 161         st,clksrc = <
 162                 CLK_MPU_PLL1P
 163                 CLK_AXI_PLL2P
 164                 CLK_MCU_PLL3P
 165                 CLK_PLL12_HSE
 166                 CLK_PLL3_HSE
 167                 CLK_PLL4_HSE
 168                 CLK_RTC_LSE
 169                 CLK_MCO1_DISABLED
 170                 CLK_MCO2_DISABLED
 171         >;
 172
 173         st,clkdiv = <
 174                 1 /*MPU*/
 175                 0 /*AXI*/
 176                 0 /*MCU*/
 177                 1 /*APB1*/
 178                 1 /*APB2*/
 179                 1 /*APB3*/
 180                 1 /*APB4*/
 181                 2 /*APB5*/
 182                 23 /*RTC*/
 183                 0 /*MCO1*/
 184                 0 /*MCO2*/
 185         >;
 186
 187         st,pkcs = <
 188                 CLK_CKPER_HSE
 189                 CLK_FMC_ACLK
 190                 CLK_QSPI_ACLK
 191                 CLK_ETH_PLL4P
 192                 CLK_SDMMC12_PLL4P
 193                 CLK_DSI_DSIPLL
 194                 CLK_STGEN_HSE
 195                 CLK_USBPHY_HSE
 196                 CLK_SPI2S1_PLL3Q
 197                 CLK_SPI2S23_PLL3Q
 198                 CLK_SPI45_HSI
 199                 CLK_SPI6_HSI
 200                 CLK_I2C46_HSI
 201                 CLK_SDMMC3_PLL4P
 202                 CLK_USBO_USBPHY
 203                 CLK_ADC_CKPER
 204                 CLK_CEC_LSE
 205                 CLK_I2C12_HSI
 206                 CLK_I2C35_HSI
 207                 CLK_UART1_HSI
 208                 CLK_UART24_HSI
 209                 CLK_UART35_HSI
 210                 CLK_UART6_HSI
 211                 CLK_UART78_HSI
 212                 CLK_SPDIF_PLL4P
 213                 CLK_FDCAN_PLL4R
 214                 CLK_SAI1_PLL3Q
 215                 CLK_SAI2_PLL3Q
 216                 CLK_SAI3_PLL3Q
 217                 CLK_SAI4_PLL3Q
 218                 CLK_RNG1_LSI
 219                 CLK_RNG2_LSI
 220                 CLK_LPTIM1_PCLK1
 221                 CLK_LPTIM23_PCLK3
 222                 CLK_LPTIM45_LSE
 223         >;
 224
 225         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 226         pll1: st,pll@0 {
 227                 compatible = "st,stm32mp1-pll";
 228                 reg = <0>;
 229                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 230                 frac = < 0x800 >;
 231                 u-boot,dm-pre-reloc;
 232         };
 233
 234         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 235         pll2: st,pll@1 {
 236                 compatible = "st,stm32mp1-pll";
 237                 reg = <1>;
 238                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 239                 frac = < 0x1400 >;
 240                 u-boot,dm-pre-reloc;
 241         };
 242
 243         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 244         pll3: st,pll@2 {
 245                 compatible = "st,stm32mp1-pll";
 246                 reg = <2>;
 247                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 248                 frac = < 0x1a04 >;
 249                 u-boot,dm-pre-reloc;
 250         };
 251
 252         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 253         pll4: st,pll@3 {
 254                 compatible = "st,stm32mp1-pll";
 255                 reg = <3>;
 256                 cfg = < 1 49 11 11 11 PQR(1,1,1) >;
 257                 u-boot,dm-pre-reloc;
 258         };
 259 };
 260
 261 &sdmmc1 {
 262         u-boot,dm-spl;
 263 };
 264
 265 &sdmmc1_b4_pins_a {
 266         u-boot,dm-spl;
 267         pins1 {
 268                 u-boot,dm-spl;
 269         };
 270         pins2 {
 271                 u-boot,dm-spl;
 272         };
 273 };
 274
 275 &sdmmc1_dir_pins_a {
 276         u-boot,dm-spl;
 277         pins1 {
 278                 u-boot,dm-spl;
 279         };
 280         pins2 {
 281                 u-boot,dm-spl;
 282         };
 283 };
 284
 285 &sdmmc2 {
 286         u-boot,dm-spl;
 287 };
 288
 289 &sdmmc2_b4_pins_a {
 290         u-boot,dm-spl;
 291         pins {
 292                 u-boot,dm-spl;
 293         };
 294 };
 295
 296 &sdmmc2_d47_pins_a {
 297         u-boot,dm-spl;
 298         pins {
 299                 u-boot,dm-spl;
 300         };
 301 };
 302
 303 &uart4 {
 304         u-boot,dm-pre-reloc;
 305 };
 306
 307 &uart4_pins_a {
 308         u-boot,dm-pre-reloc;
 309         pins1 {
 310                 u-boot,dm-pre-reloc;
 311         };
 312         pins2 {
 313                 u-boot,dm-pre-reloc;
 314                 /* pull-up on rx to avoid floating level */
 315                 bias-pull-up;
 316         };
 317 };