1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019 Marek Vasut <marex@denx.de>
6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
7 #include "stm32mp15-u-boot.dtsi"
8 #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
9 #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
10 #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
24 u-boot,boot-led = "heartbeat";
25 u-boot,error-led = "error";
26 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
27 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
28 dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>;
29 dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>;
35 gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
36 default-state = "off";
45 /* This is actually on FMC2, but we do not have bus driver for that */
46 ksz8851: ks8851mll@64000000 {
47 compatible = "micrel,ks8851-mll";
48 reg = <0x64000000 0x20000>;
57 line-name = "spi-nor-nwp";
73 /* These should bound to FMC2 bus driver, but we do not have one */
74 pinctrl-0 = <&fmc_pins_b>;
75 pinctrl-1 = <&fmc_sleep_pins_b>;
76 pinctrl-names = "default", "sleep";
80 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
81 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
82 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
83 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
84 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
85 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
86 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
87 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
88 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
89 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
90 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
91 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
92 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
93 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
94 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
95 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
96 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
97 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
98 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
99 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
100 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
107 fmc_sleep_pins_b: fmc-sleep-0 {
109 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
110 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
111 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
112 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
113 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
114 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
115 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
116 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
117 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
118 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
119 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
120 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
121 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
122 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
123 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
124 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
125 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
126 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
127 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
128 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
129 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
238 /* VCO = 1300.0 MHz => P = 650 (CPU) */
240 compatible = "st,stm32mp1-pll";
242 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
247 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
249 compatible = "st,stm32mp1-pll";
251 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
256 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
258 compatible = "st,stm32mp1-pll";
260 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
265 /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
267 compatible = "st,stm32mp1-pll";
269 cfg = < 1 49 11 11 11 PQR(1,1,1) >;
327 /* pull-up on rx to avoid floating level */