arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019 Marek Vasut <marex@denx.de>
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp157-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c1 = &i2c2;
  13                 i2c3 = &i2c4;
  14                 i2c4 = &i2c5;
  15                 mmc0 = &sdmmc1;
  16                 mmc1 = &sdmmc2;
  17                 spi0 = &qspi;
  18                 usb0 = &usbotg_hs;
  19         };
  20
  21         config {
  22                 u-boot,boot-led = "heartbeat";
  23                 u-boot,error-led = "error";
  24                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  25                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  26         };
  27
  28         led {
  29                 red {
  30                         label = "error";
  31                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  32                         default-state = "off";
  33                         status = "okay";
  34                 };
  35
  36                 blue {
  37                         default-state = "on";
  38                 };
  39         };
  40 };
  41
  42 &i2c4 {
  43         u-boot,dm-pre-reloc;
  44 };
  45
  46 &i2c4_pins_a {
  47         u-boot,dm-pre-reloc;
  48         pins {
  49                 u-boot,dm-pre-reloc;
  50         };
  51 };
  52
  53 &pmic {
  54         u-boot,dm-pre-reloc;
  55 };
  56
  57 &flash0 {
  58         u-boot,dm-spl;
  59 };
  60
  61 &qspi {
  62         u-boot,dm-spl;
  63 };
  64
  65 &qspi_clk_pins_a {
  66         u-boot,dm-spl;
  67         pins {
  68                 u-boot,dm-spl;
  69         };
  70 };
  71
  72 &qspi_bk1_pins_a {
  73         u-boot,dm-spl;
  74         pins1 {
  75                 u-boot,dm-spl;
  76         };
  77         pins2 {
  78                 u-boot,dm-spl;
  79         };
  80 };
  81
  82 &qspi_bk2_pins_a {
  83         u-boot,dm-spl;
  84         pins1 {
  85                 u-boot,dm-spl;
  86         };
  87         pins2 {
  88                 u-boot,dm-spl;
  89         };
  90 };
  91
  92 &rcc {
  93         st,clksrc = <
  94                 CLK_MPU_PLL1P
  95                 CLK_AXI_PLL2P
  96                 CLK_MCU_PLL3P
  97                 CLK_PLL12_HSE
  98                 CLK_PLL3_HSE
  99                 CLK_PLL4_HSE
 100                 CLK_RTC_LSE
 101                 CLK_MCO1_DISABLED
 102                 CLK_MCO2_DISABLED
 103         >;
 104
 105         st,clkdiv = <
 106                 1 /*MPU*/
 107                 0 /*AXI*/
 108                 0 /*MCU*/
 109                 1 /*APB1*/
 110                 1 /*APB2*/
 111                 1 /*APB3*/
 112                 1 /*APB4*/
 113                 2 /*APB5*/
 114                 23 /*RTC*/
 115                 0 /*MCO1*/
 116                 0 /*MCO2*/
 117         >;
 118
 119         st,pkcs = <
 120                 CLK_CKPER_HSE
 121                 CLK_FMC_ACLK
 122                 CLK_QSPI_ACLK
 123                 CLK_ETH_PLL4P
 124                 CLK_SDMMC12_PLL4P
 125                 CLK_DSI_DSIPLL
 126                 CLK_STGEN_HSE
 127                 CLK_USBPHY_HSE
 128                 CLK_SPI2S1_PLL3Q
 129                 CLK_SPI2S23_PLL3Q
 130                 CLK_SPI45_HSI
 131                 CLK_SPI6_HSI
 132                 CLK_I2C46_HSI
 133                 CLK_SDMMC3_PLL4P
 134                 CLK_USBO_USBPHY
 135                 CLK_ADC_CKPER
 136                 CLK_CEC_LSE
 137                 CLK_I2C12_HSI
 138                 CLK_I2C35_HSI
 139                 CLK_UART1_HSI
 140                 CLK_UART24_HSI
 141                 CLK_UART35_HSI
 142                 CLK_UART6_HSI
 143                 CLK_UART78_HSI
 144                 CLK_SPDIF_PLL4P
 145                 CLK_FDCAN_PLL4R
 146                 CLK_SAI1_PLL3Q
 147                 CLK_SAI2_PLL3Q
 148                 CLK_SAI3_PLL3Q
 149                 CLK_SAI4_PLL3Q
 150                 CLK_RNG1_LSI
 151                 CLK_RNG2_LSI
 152                 CLK_LPTIM1_PCLK1
 153                 CLK_LPTIM23_PCLK3
 154                 CLK_LPTIM45_LSE
 155         >;
 156
 157         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 158         pll1: st,pll@0 {
 159                 compatible = "st,stm32mp1-pll";
 160                 reg = <0>;
 161                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 162                 frac = < 0x800 >;
 163                 u-boot,dm-pre-reloc;
 164         };
 165
 166         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 167         pll2: st,pll@1 {
 168                 compatible = "st,stm32mp1-pll";
 169                 reg = <1>;
 170                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 171                 frac = < 0x1400 >;
 172                 u-boot,dm-pre-reloc;
 173         };
 174
 175         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 176         pll3: st,pll@2 {
 177                 compatible = "st,stm32mp1-pll";
 178                 reg = <2>;
 179                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 180                 frac = < 0x1a04 >;
 181                 u-boot,dm-pre-reloc;
 182         };
 183
 184         /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
 185         pll4: st,pll@3 {
 186                 compatible = "st,stm32mp1-pll";
 187                 reg = <3>;
 188                 cfg = < 1 49 11 11 11 PQR(1,1,1) >;
 189                 u-boot,dm-pre-reloc;
 190         };
 191 };
 192
 193 &sdmmc1 {
 194         u-boot,dm-spl;
 195 };
 196
 197 &sdmmc1_b4_pins_a {
 198         u-boot,dm-spl;
 199         pins {
 200                 u-boot,dm-spl;
 201         };
 202 };
 203
 204 &sdmmc1_dir_pins_a {
 205         u-boot,dm-spl;
 206         pins1 {
 207                 u-boot,dm-spl;
 208         };
 209         pins2 {
 210                 u-boot,dm-spl;
 211         };
 212 };
 213
 214 &sdmmc2 {
 215         u-boot,dm-spl;
 216 };
 217
 218 &sdmmc2_b4_pins_a {
 219         u-boot,dm-spl;
 220         pins {
 221                 u-boot,dm-spl;
 222         };
 223 };
 224
 225 &sdmmc2_d47_pins_a {
 226         u-boot,dm-spl;
 227         pins {
 228                 u-boot,dm-spl;
 229         };
 230 };
 231
 232 &uart4 {
 233         u-boot,dm-pre-reloc;
 234 };
 235
 236 &uart4_pins_a {
 237         u-boot,dm-pre-reloc;
 238         pins1 {
 239                 u-boot,dm-pre-reloc;
 240         };
 241         pins2 {
 242                 u-boot,dm-pre-reloc;
 243                 /* pull-up on rx to avoid floating level */
 244                 bias-pull-up;
 245         };
 246 };