arch/arm/dts/stm32mp157c.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci-1.0";
  33                 method = "smc";
  34                 cpu_off = <0x84000002>;
  35                 cpu_on = <0x84000003>;
  36         };
  37
  38         aliases {
  39                 gpio0 = &gpioa;
  40                 gpio1 = &gpiob;
  41                 gpio2 = &gpioc;
  42                 gpio3 = &gpiod;
  43                 gpio4 = &gpioe;
  44                 gpio5 = &gpiof;
  45                 gpio6 = &gpiog;
  46                 gpio7 = &gpioh;
  47                 gpio8 = &gpioi;
  48                 gpio9 = &gpioj;
  49                 gpio10 = &gpiok;
  50                 serial0 = &usart1;
  51                 serial1 = &usart2;
  52                 serial2 = &usart3;
  53                 serial3 = &uart4;
  54                 serial4 = &uart5;
  55                 serial5 = &usart6;
  56                 serial6 = &uart7;
  57                 serial7 = &uart8;
  58         };
  59
  60         intc: interrupt-controller@a0021000 {
  61                 compatible = "arm,cortex-a7-gic";
  62                 #interrupt-cells = <3>;
  63                 interrupt-controller;
  64                 reg = <0xa0021000 0x1000>,
  65                       <0xa0022000 0x2000>;
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv7-timer";
  70                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  71                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  72                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  74                 interrupt-parent = <&intc>;
  75         };
  76
  77         clocks {
  78                 clk_hse: clk-hse {
  79                         #clock-cells = <0>;
  80                         compatible = "fixed-clock";
  81                         clock-frequency = <24000000>;
  82                 };
  83
  84                 clk_hsi: clk-hsi {
  85                         #clock-cells = <0>;
  86                         compatible = "fixed-clock";
  87                         clock-frequency = <64000000>;
  88                 };
  89
  90                 clk_lse: clk-lse {
  91                         #clock-cells = <0>;
  92                         compatible = "fixed-clock";
  93                         clock-frequency = <32768>;
  94                 };
  95
  96                 clk_lsi: clk-lsi {
  97                         #clock-cells = <0>;
  98                         compatible = "fixed-clock";
  99                         clock-frequency = <32000>;
 100                 };
 101
 102                 clk_csi: clk-csi {
 103                         #clock-cells = <0>;
 104                         compatible = "fixed-clock";
 105                         clock-frequency = <4000000>;
 106                 };
 107         };
 108
 109         soc {
 110                 compatible = "simple-bus";
 111                 #address-cells = <1>;
 112                 #size-cells = <1>;
 113                 interrupt-parent = <&intc>;
 114                 ranges;
 115
 116                 timers2: timer@40000000 {
 117                         #address-cells = <1>;
 118                         #size-cells = <0>;
 119                         compatible = "st,stm32-timers";
 120                         reg = <0x40000000 0x400>;
 121                         clocks = <&rcc TIM2_K>;
 122                         clock-names = "int";
 123                         status = "disabled";
 124
 125                         pwm {
 126                                 compatible = "st,stm32-pwm";
 127                                 status = "disabled";
 128                         };
 129
 130                         timer@1 {
 131                                 compatible = "st,stm32h7-timer-trigger";
 132                                 reg = <1>;
 133                                 status = "disabled";
 134                         };
 135                 };
 136
 137                 timers3: timer@40001000 {
 138                         #address-cells = <1>;
 139                         #size-cells = <0>;
 140                         compatible = "st,stm32-timers";
 141                         reg = <0x40001000 0x400>;
 142                         clocks = <&rcc TIM3_K>;
 143                         clock-names = "int";
 144                         status = "disabled";
 145
 146                         pwm {
 147                                 compatible = "st,stm32-pwm";
 148                                 status = "disabled";
 149                         };
 150
 151                         timer@2 {
 152                                 compatible = "st,stm32h7-timer-trigger";
 153                                 reg = <2>;
 154                                 status = "disabled";
 155                         };
 156                 };
 157
 158                 timers4: timer@40002000 {
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         compatible = "st,stm32-timers";
 162                         reg = <0x40002000 0x400>;
 163                         clocks = <&rcc TIM4_K>;
 164                         clock-names = "int";
 165                         status = "disabled";
 166
 167                         pwm {
 168                                 compatible = "st,stm32-pwm";
 169                                 status = "disabled";
 170                         };
 171
 172                         timer@3 {
 173                                 compatible = "st,stm32h7-timer-trigger";
 174                                 reg = <3>;
 175                                 status = "disabled";
 176                         };
 177                 };
 178
 179                 timers5: timer@40003000 {
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         compatible = "st,stm32-timers";
 183                         reg = <0x40003000 0x400>;
 184                         clocks = <&rcc TIM5_K>;
 185                         clock-names = "int";
 186                         status = "disabled";
 187
 188                         pwm {
 189                                 compatible = "st,stm32-pwm";
 190                                 status = "disabled";
 191                         };
 192
 193                         timer@4 {
 194                                 compatible = "st,stm32h7-timer-trigger";
 195                                 reg = <4>;
 196                                 status = "disabled";
 197                         };
 198                 };
 199
 200                 timers6: timer@40004000 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         compatible = "st,stm32-timers";
 204                         reg = <0x40004000 0x400>;
 205                         clocks = <&rcc TIM6_K>;
 206                         clock-names = "int";
 207                         status = "disabled";
 208
 209                         timer@5 {
 210                                 compatible = "st,stm32h7-timer-trigger";
 211                                 reg = <5>;
 212                                 status = "disabled";
 213                         };
 214                 };
 215
 216                 timers7: timer@40005000 {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         compatible = "st,stm32-timers";
 220                         reg = <0x40005000 0x400>;
 221                         clocks = <&rcc TIM7_K>;
 222                         clock-names = "int";
 223                         status = "disabled";
 224
 225                         timer@6 {
 226                                 compatible = "st,stm32h7-timer-trigger";
 227                                 reg = <6>;
 228                                 status = "disabled";
 229                         };
 230                 };
 231
 232                 timers12: timer@40006000 {
 233                         #address-cells = <1>;
 234                         #size-cells = <0>;
 235                         compatible = "st,stm32-timers";
 236                         reg = <0x40006000 0x400>;
 237                         clocks = <&rcc TIM12_K>;
 238                         clock-names = "int";
 239                         status = "disabled";
 240
 241                         pwm {
 242                                 compatible = "st,stm32-pwm";
 243                                 status = "disabled";
 244                         };
 245
 246                         timer@11 {
 247                                 compatible = "st,stm32h7-timer-trigger";
 248                                 reg = <11>;
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 timers13: timer@40007000 {
 254                         #address-cells = <1>;
 255                         #size-cells = <0>;
 256                         compatible = "st,stm32-timers";
 257                         reg = <0x40007000 0x400>;
 258                         clocks = <&rcc TIM13_K>;
 259                         clock-names = "int";
 260                         status = "disabled";
 261
 262                         pwm {
 263                                 compatible = "st,stm32-pwm";
 264                                 status = "disabled";
 265                         };
 266
 267                         timer@12 {
 268                                 compatible = "st,stm32h7-timer-trigger";
 269                                 reg = <12>;
 270                                 status = "disabled";
 271                         };
 272                 };
 273
 274                 timers14: timer@40008000 {
 275                         #address-cells = <1>;
 276                         #size-cells = <0>;
 277                         compatible = "st,stm32-timers";
 278                         reg = <0x40008000 0x400>;
 279                         clocks = <&rcc TIM14_K>;
 280                         clock-names = "int";
 281                         status = "disabled";
 282
 283                         pwm {
 284                                 compatible = "st,stm32-pwm";
 285                                 status = "disabled";
 286                         };
 287
 288                         timer@13 {
 289                                 compatible = "st,stm32h7-timer-trigger";
 290                                 reg = <13>;
 291                                 status = "disabled";
 292                         };
 293                 };
 294
 295                 lptimer1: timer@40009000 {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         compatible = "st,stm32-lptimer";
 299                         reg = <0x40009000 0x400>;
 300                         clocks = <&rcc LPTIM1_K>;
 301                         clock-names = "mux";
 302                         status = "disabled";
 303
 304                         pwm {
 305                                 compatible = "st,stm32-pwm-lp";
 306                                 #pwm-cells = <3>;
 307                                 status = "disabled";
 308                         };
 309
 310                         trigger@0 {
 311                                 compatible = "st,stm32-lptimer-trigger";
 312                                 reg = <0>;
 313                                 status = "disabled";
 314                         };
 315
 316                         counter {
 317                                 compatible = "st,stm32-lptimer-counter";
 318                                 status = "disabled";
 319                         };
 320                 };
 321
 322                 spi2: spi@4000b000 {
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         compatible = "st,stm32h7-spi";
 326                         reg = <0x4000b000 0x400>;
 327                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&rcc SPI2_K>;
 329                         resets = <&rcc SPI2_R>;
 330                         dmas = <&dmamux1 39 0x400 0x05>,
 331                                <&dmamux1 40 0x400 0x05>;
 332                         dma-names = "rx", "tx";
 333                         status = "disabled";
 334                 };
 335
 336                 spi3: spi@4000c000 {
 337                         #address-cells = <1>;
 338                         #size-cells = <0>;
 339                         compatible = "st,stm32h7-spi";
 340                         reg = <0x4000c000 0x400>;
 341                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&rcc SPI3_K>;
 343                         resets = <&rcc SPI3_R>;
 344                         dmas = <&dmamux1 61 0x400 0x05>,
 345                                <&dmamux1 62 0x400 0x05>;
 346                         dma-names = "rx", "tx";
 347                         status = "disabled";
 348                 };
 349
 350                 usart2: serial@4000e000 {
 351                         compatible = "st,stm32h7-uart";
 352                         reg = <0x4000e000 0x400>;
 353                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&rcc USART2_K>;
 355                         status = "disabled";
 356                 };
 357
 358                 usart3: serial@4000f000 {
 359                         compatible = "st,stm32h7-uart";
 360                         reg = <0x4000f000 0x400>;
 361                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 362                         clocks = <&rcc USART3_K>;
 363                         status = "disabled";
 364                 };
 365
 366                 uart4: serial@40010000 {
 367                         compatible = "st,stm32h7-uart";
 368                         reg = <0x40010000 0x400>;
 369                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&rcc UART4_K>;
 371                         status = "disabled";
 372                 };
 373
 374                 uart5: serial@40011000 {
 375                         compatible = "st,stm32h7-uart";
 376                         reg = <0x40011000 0x400>;
 377                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&rcc UART5_K>;
 379                         status = "disabled";
 380                 };
 381
 382                 i2c1: i2c@40012000 {
 383                         compatible = "st,stm32f7-i2c";
 384                         reg = <0x40012000 0x400>;
 385                         interrupt-names = "event", "error";
 386                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&rcc I2C1_K>;
 389                         resets = <&rcc I2C1_R>;
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         status = "disabled";
 393                 };
 394
 395                 i2c2: i2c@40013000 {
 396                         compatible = "st,stm32f7-i2c";
 397                         reg = <0x40013000 0x400>;
 398                         interrupt-names = "event", "error";
 399                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 400                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 401                         clocks = <&rcc I2C2_K>;
 402                         resets = <&rcc I2C2_R>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         status = "disabled";
 406                 };
 407
 408                 i2c3: i2c@40014000 {
 409                         compatible = "st,stm32f7-i2c";
 410                         reg = <0x40014000 0x400>;
 411                         interrupt-names = "event", "error";
 412                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 413                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&rcc I2C3_K>;
 415                         resets = <&rcc I2C3_R>;
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         status = "disabled";
 419                 };
 420
 421                 i2c5: i2c@40015000 {
 422                         compatible = "st,stm32f7-i2c";
 423                         reg = <0x40015000 0x400>;
 424                         interrupt-names = "event", "error";
 425                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 426                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 427                         clocks = <&rcc I2C5_K>;
 428                         resets = <&rcc I2C5_R>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         status = "disabled";
 432                 };
 433
 434                 cec: cec@40016000 {
 435                         compatible = "st,stm32-cec";
 436                         reg = <0x40016000 0x400>;
 437                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&rcc CEC_K>, <&clk_lse>;
 439                         clock-names = "cec", "hdmi-cec";
 440                         status = "disabled";
 441                 };
 442
 443                 dac: dac@40017000 {
 444                         compatible = "st,stm32h7-dac-core";
 445                         reg = <0x40017000 0x400>;
 446                         clocks = <&rcc DAC12>;
 447                         clock-names = "pclk";
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         status = "disabled";
 451
 452                         dac1: dac@1 {
 453                                 compatible = "st,stm32-dac";
 454                                 #io-channels-cells = <1>;
 455                                 reg = <1>;
 456                                 status = "disabled";
 457                         };
 458
 459                         dac2: dac@2 {
 460                                 compatible = "st,stm32-dac";
 461                                 #io-channels-cells = <1>;
 462                                 reg = <2>;
 463                                 status = "disabled";
 464                         };
 465                 };
 466
 467                 uart7: serial@40018000 {
 468                         compatible = "st,stm32h7-uart";
 469                         reg = <0x40018000 0x400>;
 470                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&rcc UART7_K>;
 472                         status = "disabled";
 473                 };
 474
 475                 uart8: serial@40019000 {
 476                         compatible = "st,stm32h7-uart";
 477                         reg = <0x40019000 0x400>;
 478                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&rcc UART8_K>;
 480                         status = "disabled";
 481                 };
 482
 483                 timers1: timer@44000000 {
 484                         #address-cells = <1>;
 485                         #size-cells = <0>;
 486                         compatible = "st,stm32-timers";
 487                         reg = <0x44000000 0x400>;
 488                         clocks = <&rcc TIM1_K>;
 489                         clock-names = "int";
 490                         status = "disabled";
 491
 492                         pwm {
 493                                 compatible = "st,stm32-pwm";
 494                                 status = "disabled";
 495                         };
 496
 497                         timer@0 {
 498                                 compatible = "st,stm32h7-timer-trigger";
 499                                 reg = <0>;
 500                                 status = "disabled";
 501                         };
 502                 };
 503
 504                 timers8: timer@44001000 {
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                         compatible = "st,stm32-timers";
 508                         reg = <0x44001000 0x400>;
 509                         clocks = <&rcc TIM8_K>;
 510                         clock-names = "int";
 511                         status = "disabled";
 512
 513                         pwm {
 514                                 compatible = "st,stm32-pwm";
 515                                 status = "disabled";
 516                         };
 517
 518                         timer@7 {
 519                                 compatible = "st,stm32h7-timer-trigger";
 520                                 reg = <7>;
 521                                 status = "disabled";
 522                         };
 523                 };
 524
 525                 usart6: serial@44003000 {
 526                         compatible = "st,stm32h7-uart";
 527                         reg = <0x44003000 0x400>;
 528                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&rcc USART6_K>;
 530                         status = "disabled";
 531                 };
 532
 533                 spi1: spi@44004000 {
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         compatible = "st,stm32h7-spi";
 537                         reg = <0x44004000 0x400>;
 538                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&rcc SPI1_K>;
 540                         resets = <&rcc SPI1_R>;
 541                         dmas = <&dmamux1 37 0x400 0x05>,
 542                                <&dmamux1 38 0x400 0x05>;
 543                         dma-names = "rx", "tx";
 544                         status = "disabled";
 545                 };
 546
 547                 spi4: spi@44005000 {
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         compatible = "st,stm32h7-spi";
 551                         reg = <0x44005000 0x400>;
 552                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 553                         clocks = <&rcc SPI4_K>;
 554                         resets = <&rcc SPI4_R>;
 555                         dmas = <&dmamux1 83 0x400 0x05>,
 556                                <&dmamux1 84 0x400 0x05>;
 557                         dma-names = "rx", "tx";
 558                         status = "disabled";
 559                 };
 560
 561                 timers15: timer@44006000 {
 562                         #address-cells = <1>;
 563                         #size-cells = <0>;
 564                         compatible = "st,stm32-timers";
 565                         reg = <0x44006000 0x400>;
 566                         clocks = <&rcc TIM15_K>;
 567                         clock-names = "int";
 568                         status = "disabled";
 569
 570                         pwm {
 571                                 compatible = "st,stm32-pwm";
 572                                 status = "disabled";
 573                         };
 574
 575                         timer@14 {
 576                                 compatible = "st,stm32h7-timer-trigger";
 577                                 reg = <14>;
 578                                 status = "disabled";
 579                         };
 580                 };
 581
 582                 timers16: timer@44007000 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         compatible = "st,stm32-timers";
 586                         reg = <0x44007000 0x400>;
 587                         clocks = <&rcc TIM16_K>;
 588                         clock-names = "int";
 589                         status = "disabled";
 590
 591                         pwm {
 592                                 compatible = "st,stm32-pwm";
 593                                 status = "disabled";
 594                         };
 595                         timer@15 {
 596                                 compatible = "st,stm32h7-timer-trigger";
 597                                 reg = <15>;
 598                                 status = "disabled";
 599                         };
 600                 };
 601
 602                 timers17: timer@44008000 {
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         compatible = "st,stm32-timers";
 606                         reg = <0x44008000 0x400>;
 607                         clocks = <&rcc TIM17_K>;
 608                         clock-names = "int";
 609                         status = "disabled";
 610
 611                         pwm {
 612                                 compatible = "st,stm32-pwm";
 613                                 status = "disabled";
 614                         };
 615
 616                         timer@16 {
 617                                 compatible = "st,stm32h7-timer-trigger";
 618                                 reg = <16>;
 619                                 status = "disabled";
 620                         };
 621                 };
 622
 623                 spi5: spi@44009000 {
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626                         compatible = "st,stm32h7-spi";
 627                         reg = <0x44009000 0x400>;
 628                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 629                         clocks = <&rcc SPI5_K>;
 630                         resets = <&rcc SPI5_R>;
 631                         dmas = <&dmamux1 85 0x400 0x05>,
 632                                <&dmamux1 86 0x400 0x05>;
 633                         dma-names = "rx", "tx";
 634                         status = "disabled";
 635                 };
 636
 637                 dfsdm: dfsdm@4400d000 {
 638                         compatible = "st,stm32mp1-dfsdm";
 639                         reg = <0x4400d000 0x800>;
 640                         clocks = <&rcc DFSDM_K>;
 641                         clock-names = "dfsdm";
 642                         #address-cells = <1>;
 643                         #size-cells = <0>;
 644                         status = "disabled";
 645
 646                         dfsdm0: filter@0 {
 647                                 compatible = "st,stm32-dfsdm-adc";
 648                                 #io-channel-cells = <1>;
 649                                 reg = <0>;
 650                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 651                                 dmas = <&dmamux1 101 0x400 0x01>;
 652                                 dma-names = "rx";
 653                                 status = "disabled";
 654                         };
 655
 656                         dfsdm1: filter@1 {
 657                                 compatible = "st,stm32-dfsdm-adc";
 658                                 #io-channel-cells = <1>;
 659                                 reg = <1>;
 660                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 661                                 dmas = <&dmamux1 102 0x400 0x01>;
 662                                 dma-names = "rx";
 663                                 status = "disabled";
 664                         };
 665
 666                         dfsdm2: filter@2 {
 667                                 compatible = "st,stm32-dfsdm-adc";
 668                                 #io-channel-cells = <1>;
 669                                 reg = <2>;
 670                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 671                                 dmas = <&dmamux1 103 0x400 0x01>;
 672                                 dma-names = "rx";
 673                                 status = "disabled";
 674                         };
 675
 676                         dfsdm3: filter@3 {
 677                                 compatible = "st,stm32-dfsdm-adc";
 678                                 #io-channel-cells = <1>;
 679                                 reg = <3>;
 680                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 681                                 dmas = <&dmamux1 104 0x400 0x01>;
 682                                 dma-names = "rx";
 683                                 status = "disabled";
 684                         };
 685
 686                         dfsdm4: filter@4 {
 687                                 compatible = "st,stm32-dfsdm-adc";
 688                                 #io-channel-cells = <1>;
 689                                 reg = <4>;
 690                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 691                                 dmas = <&dmamux1 91 0x400 0x01>;
 692                                 dma-names = "rx";
 693                                 status = "disabled";
 694                         };
 695
 696                         dfsdm5: filter@5 {
 697                                 compatible = "st,stm32-dfsdm-adc";
 698                                 #io-channel-cells = <1>;
 699                                 reg = <5>;
 700                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 701                                 dmas = <&dmamux1 92 0x400 0x01>;
 702                                 dma-names = "rx";
 703                                 status = "disabled";
 704                         };
 705                 };
 706
 707                 m_can1: can@4400e000 {
 708                         compatible = "bosch,m_can";
 709                         reg = <0x4400e000 0x400>, <0x44011000 0x2800>;
 710                         reg-names = "m_can", "message_ram";
 711                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 713                         interrupt-names = "int0", "int1";
 714                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 715                         clock-names = "hclk", "cclk";
 716                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 717                         status = "disabled";
 718                 };
 719
 720                 m_can2: can@4400f000 {
 721                         compatible = "bosch,m_can";
 722                         reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
 723                         reg-names = "m_can", "message_ram";
 724                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 725                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 726                         interrupt-names = "int0", "int1";
 727                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 728                         clock-names = "hclk", "cclk";
 729                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 730                         status = "disabled";
 731                 };
 732
 733                 dma1: dma@48000000 {
 734                         compatible = "st,stm32-dma";
 735                         reg = <0x48000000 0x400>;
 736                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&rcc DMA1>;
 745                         #dma-cells = <4>;
 746                         st,mem2mem;
 747                         dma-requests = <8>;
 748                 };
 749
 750                 dma2: dma@48001000 {
 751                         compatible = "st,stm32-dma";
 752                         reg = <0x48001000 0x400>;
 753                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 759                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 760                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&rcc DMA2>;
 762                         #dma-cells = <4>;
 763                         st,mem2mem;
 764                         dma-requests = <8>;
 765                 };
 766
 767                 dmamux1: dma-router@48002000 {
 768                         compatible = "st,stm32h7-dmamux";
 769                         reg = <0x48002000 0x1c>;
 770                         #dma-cells = <3>;
 771                         dma-requests = <128>;
 772                         dma-masters = <&dma1 &dma2>;
 773                         dma-channels = <16>;
 774                         clocks = <&rcc DMAMUX>;
 775                 };
 776
 777                 adc: adc@48003000 {
 778                         compatible = "st,stm32mp1-adc-core";
 779                         reg = <0x48003000 0x400>;
 780                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 781                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 782                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
 783                         clock-names = "bus", "adc";
 784                         interrupt-controller;
 785                         #interrupt-cells = <1>;
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788                         status = "disabled";
 789
 790                         adc1: adc@0 {
 791                                 compatible = "st,stm32mp1-adc";
 792                                 #io-channel-cells = <1>;
 793                                 reg = <0x0>;
 794                                 interrupt-parent = <&adc>;
 795                                 interrupts = <0>;
 796                                 dmas = <&dmamux1 9 0x400 0x01>;
 797                                 dma-names = "rx";
 798                                 status = "disabled";
 799                         };
 800
 801                         adc2: adc@100 {
 802                                 compatible = "st,stm32mp1-adc";
 803                                 #io-channel-cells = <1>;
 804                                 reg = <0x100>;
 805                                 interrupt-parent = <&adc>;
 806                                 interrupts = <1>;
 807                                 dmas = <&dmamux1 10 0x400 0x01>;
 808                                 dma-names = "rx";
 809                                 status = "disabled";
 810                         };
 811                 };
 812
 813                 sdmmc3: sdmmc@48004000 {
 814                         compatible = "st,stm32-sdmmc2";
 815                         reg = <0x48004000 0x400>, <0x48005000 0x400>;
 816                         reg-names = "sdmmc", "delay";
 817                         interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
 818                         clocks = <&rcc SDMMC3_K>;
 819                         resets = <&rcc SDMMC3_R>;
 820                         st,idma = <1>;
 821                         cap-sd-highspeed;
 822                         cap-mmc-highspeed;
 823                         max-frequency = <120000000>;
 824                         status = "disabled";
 825                 };
 826
 827                 usbotg_hs: usb-otg@49000000 {
 828                         compatible = "st,stm32mp1-hsotg", "snps,dwc2";
 829                         reg = <0x49000000 0x10000>;
 830                         clocks = <&rcc USBO_K>;
 831                         clock-names = "otg";
 832                         resets = <&rcc USBO_R>;
 833                         reset-names = "dwc2";
 834                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 835                         g-rx-fifo-size = <256>;
 836                         g-np-tx-fifo-size = <32>;
 837                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 838                         dr_mode = "otg";
 839                         usb33d-supply = <&usb33>;
 840                         status = "disabled";
 841                 };
 842
 843                 hwspinlock: hwspinlock@4c000000 {
 844                         compatible = "st,stm32-hwspinlock";
 845                         #hwlock-cells = <1>;
 846                         reg = <0x4c000000 0x400>;
 847                         clocks = <&rcc HSEM>;
 848                         clock-names = "hwspinlock";
 849                         status = "disabled";
 850                 };
 851
 852                 ipcc: mailbox@4c001000 {
 853                         compatible = "st,stm32mp1-ipcc";
 854                         #mbox-cells = <1>;
 855                         reg = <0x4c001000 0x400>;
 856                         st,proc-id = <0>;
 857                         interrupts-extended =
 858                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 859                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 860                         interrupt-names = "rx", "tx";
 861                         clocks = <&rcc IPCC>;
 862                         status = "disabled";
 863                 };
 864
 865                 rcc: rcc@50000000 {
 866                         compatible = "st,stm32mp1-rcc", "syscon";
 867                         reg = <0x50000000 0x1000>;
 868                         #clock-cells = <1>;
 869                         #reset-cells = <1>;
 870                 };
 871
 872                 rcc_reboot: rcc-reboot@50000000 {
 873                         compatible = "syscon-reboot";
 874                         regmap = <&rcc>;
 875                         offset = <0x404>;
 876                         mask = <0x1>;
 877                 };
 878
 879                 pwr: pwr@50001000 {
 880                         compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
 881                         reg = <0x50001000 0x400>;
 882                         system-power-controller;
 883                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 884                         st,sysrcc = <&rcc>;
 885                         clocks = <&rcc PLL2_R>;
 886                         clock-names = "phyclk";
 887
 888                         pwr-regulators@c {
 889                                 compatible = "st,stm32mp1,pwr-reg";
 890                                 st,tzcr = <&rcc 0x0 0x1>;
 891
 892                                 reg11: reg11 {
 893                                         regulator-name = "reg11";
 894                                         regulator-min-microvolt = <1100000>;
 895                                         regulator-max-microvolt = <1100000>;
 896                                 };
 897
 898                                 reg18: reg18 {
 899                                         regulator-name = "reg18";
 900                                         regulator-min-microvolt = <1800000>;
 901                                         regulator-max-microvolt = <1800000>;
 902                                 };
 903
 904                                 usb33: usb33 {
 905                                         regulator-name = "usb33";
 906                                         regulator-min-microvolt = <3300000>;
 907                                         regulator-max-microvolt = <3300000>;
 908                                 };
 909                         };
 910                 };
 911
 912                 exti: interrupt-controller@5000d000 {
 913                         compatible = "st,stm32mp1-exti", "syscon";
 914                         interrupt-controller;
 915                         #interrupt-cells = <2>;
 916                         reg = <0x5000d000 0x400>;
 917                 };
 918
 919                 syscfg: syscon@50020000 {
 920                         compatible = "st,stm32mp157-syscfg", "syscon";
 921                         reg = <0x50020000 0x400>;
 922                 };
 923
 924                 lptimer2: timer@50021000 {
 925                         #address-cells = <1>;
 926                         #size-cells = <0>;
 927                         compatible = "st,stm32-lptimer";
 928                         reg = <0x50021000 0x400>;
 929                         clocks = <&rcc LPTIM2_K>;
 930                         clock-names = "mux";
 931                         status = "disabled";
 932
 933                         pwm {
 934                                 compatible = "st,stm32-pwm-lp";
 935                                 #pwm-cells = <3>;
 936                                 status = "disabled";
 937                         };
 938
 939                         trigger@1 {
 940                                 compatible = "st,stm32-lptimer-trigger";
 941                                 reg = <1>;
 942                                 status = "disabled";
 943                         };
 944
 945                         counter {
 946                                 compatible = "st,stm32-lptimer-counter";
 947                                 status = "disabled";
 948                         };
 949                 };
 950
 951                 lptimer3: timer@50022000 {
 952                         #address-cells = <1>;
 953                         #size-cells = <0>;
 954                         compatible = "st,stm32-lptimer";
 955                         reg = <0x50022000 0x400>;
 956                         clocks = <&rcc LPTIM3_K>;
 957                         clock-names = "mux";
 958                         status = "disabled";
 959
 960                         pwm {
 961                                 compatible = "st,stm32-pwm-lp";
 962                                 #pwm-cells = <3>;
 963                                 status = "disabled";
 964                         };
 965
 966                         trigger@2 {
 967                                 compatible = "st,stm32-lptimer-trigger";
 968                                 reg = <2>;
 969                                 status = "disabled";
 970                         };
 971                 };
 972
 973                 lptimer4: timer@50023000 {
 974                         compatible = "st,stm32-lptimer";
 975                         reg = <0x50023000 0x400>;
 976                         clocks = <&rcc LPTIM4_K>;
 977                         clock-names = "mux";
 978                         status = "disabled";
 979
 980                         pwm {
 981                                 compatible = "st,stm32-pwm-lp";
 982                                 #pwm-cells = <3>;
 983                                 status = "disabled";
 984                         };
 985                 };
 986
 987                 lptimer5: timer@50024000 {
 988                         compatible = "st,stm32-lptimer";
 989                         reg = <0x50024000 0x400>;
 990                         clocks = <&rcc LPTIM5_K>;
 991                         clock-names = "mux";
 992                         status = "disabled";
 993
 994                         pwm {
 995                                 compatible = "st,stm32-pwm-lp";
 996                                 #pwm-cells = <3>;
 997                                 status = "disabled";
 998                         };
 999                 };
1000
1001                 vrefbuf: vrefbuf@50025000 {
1002                         compatible = "st,stm32-vrefbuf";
1003                         reg = <0x50025000 0x8>;
1004                         regulator-min-microvolt = <1500000>;
1005                         regulator-max-microvolt = <2500000>;
1006                         clocks = <&rcc VREF>;
1007                         status = "disabled";
1008                 };
1009
1010                 cryp1: cryp@54001000 {
1011                         compatible = "st,stm32mp1-cryp";
1012                         reg = <0x54001000 0x400>;
1013                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1014                         clocks = <&rcc CRYP1>;
1015                         resets = <&rcc CRYP1_R>;
1016                         status = "disabled";
1017                 };
1018
1019                 hash1: hash@54002000 {
1020                         compatible = "st,stm32f756-hash";
1021                         reg = <0x54002000 0x400>;
1022                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1023                         clocks = <&rcc HASH1>;
1024                         resets = <&rcc HASH1_R>;
1025                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1026                         dma-names = "in";
1027                         dma-maxburst = <2>;
1028                         status = "disabled";
1029                 };
1030
1031                 rng1: rng@54003000 {
1032                         compatible = "st,stm32-rng";
1033                         reg = <0x54003000 0x400>;
1034                         clocks = <&rcc RNG1_K>;
1035                         resets = <&rcc RNG1_R>;
1036                         status = "disabled";
1037                 };
1038
1039                 mdma1: dma@58000000 {
1040                         compatible = "st,stm32h7-mdma";
1041                         reg = <0x58000000 0x1000>;
1042                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1043                         clocks = <&rcc MDMA>;
1044                         #dma-cells = <5>;
1045                         dma-channels = <32>;
1046                         dma-requests = <48>;
1047                 };
1048
1049                 fmc: nand-controller@58002000 {
1050                         compatible = "st,stm32mp15-fmc2";
1051                         reg = <0x58002000 0x1000>,
1052                               <0x80000000 0x1000>,
1053                               <0x88010000 0x1000>,
1054                               <0x88020000 0x1000>,
1055                               <0x81000000 0x1000>,
1056                               <0x89010000 0x1000>,
1057                               <0x89020000 0x1000>;
1058                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1059                         clocks = <&rcc FMC_K>;
1060                         resets = <&rcc FMC_R>;
1061                         status = "disabled";
1062                 };
1063
1064                 qspi: spi@58003000 {
1065                         compatible = "st,stm32f469-qspi";
1066                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1067                         reg-names = "qspi", "qspi_mm";
1068                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1069                         clocks = <&rcc QSPI_K>;
1070                         resets = <&rcc QSPI_R>;
1071                         status = "disabled";
1072                 };
1073
1074                 sdmmc1: sdmmc@58005000 {
1075                         compatible = "st,stm32-sdmmc2";
1076                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
1077                         reg-names = "sdmmc", "delay";
1078                         clocks = <&rcc SDMMC1_K>;
1079                         resets = <&rcc SDMMC1_R>;
1080                         st,idma = <1>;
1081                         cap-sd-highspeed;
1082                         cap-mmc-highspeed;
1083                         max-frequency = <120000000>;
1084                         status = "disabled";
1085                 };
1086
1087                 sdmmc2: sdmmc@58007000 {
1088                         compatible = "st,stm32-sdmmc2";
1089                         reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
1090                         reg-names = "sdmmc", "delay";
1091                         interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
1092                         clocks = <&rcc SDMMC2_K>;
1093                         resets = <&rcc SDMMC2_R>;
1094                         st,idma = <1>;
1095                         cap-sd-highspeed;
1096                         cap-mmc-highspeed;
1097                         max-frequency = <120000000>;
1098                         status = "disabled";
1099                 };
1100
1101                 crc1: crc@58009000 {
1102                         compatible = "st,stm32f7-crc";
1103                         reg = <0x58009000 0x400>;
1104                         clocks = <&rcc CRC1>;
1105                         status = "disabled";
1106                 };
1107
1108                 stmmac_axi_config_0: stmmac-axi-config {
1109                         snps,wr_osr_lmt = <0x7>;
1110                         snps,rd_osr_lmt = <0x7>;
1111                         snps,blen = <0 0 0 0 16 8 4>;
1112                 };
1113
1114                 ethernet0: ethernet@5800a000 {
1115                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1116                         reg = <0x5800a000 0x2000>;
1117                         reg-names = "stmmaceth";
1118                         interrupts-extended =
1119                                 <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1120                                 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
1121                                 <&exti 70 1>;
1122                         interrupt-names = "macirq",
1123                                           "eth_wake_irq",
1124                                           "stm32_pwr_wakeup";
1125                         clock-names = "stmmaceth",
1126                                       "mac-clk-tx",
1127                                       "mac-clk-rx",
1128                                       "ethstp";
1129                         clocks = <&rcc ETHMAC>,
1130                                  <&rcc ETHTX>,
1131                                  <&rcc ETHRX>,
1132                                  <&rcc ETHSTP>;
1133                         st,syscon = <&syscfg 0x4>;
1134                         snps,mixed-burst;
1135                         snps,pbl = <2>;
1136                         snps,en-tx-lpi-clockgating;
1137                         snps,axi-config = <&stmmac_axi_config_0>;
1138                         snps,tso;
1139                         status = "disabled";
1140                 };
1141
1142                 usbh_ohci: usbh-ohci@5800c000 {
1143                         compatible = "generic-ohci";
1144                         reg = <0x5800c000 0x1000>;
1145                         clocks = <&rcc USBH>;
1146                         resets = <&rcc USBH_R>;
1147                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1148                         status = "disabled";
1149                 };
1150
1151                 usbh_ehci: usbh-ehci@5800d000 {
1152                         compatible = "generic-ehci";
1153                         reg = <0x5800d000 0x1000>;
1154                         clocks = <&rcc USBH>;
1155                         resets = <&rcc USBH_R>;
1156                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1157                         companion = <&usbh_ohci>;
1158                         status = "disabled";
1159                 };
1160
1161                 dsi: dsi@5a000000 {
1162                         compatible = "st,stm32-dsi";
1163                         reg = <0x5a000000 0x800>;
1164                         clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1165                         clock-names = "pclk", "ref", "px_clk";
1166                         resets = <&rcc DSI_R>;
1167                         reset-names = "apb";
1168                         status = "disabled";
1169                 };
1170
1171                 ltdc: display-controller@5a001000 {
1172                         compatible = "st,stm32-ltdc";
1173                         reg = <0x5a001000 0x400>;
1174                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1175                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1176                         clocks = <&rcc LTDC_PX>;
1177                         clock-names = "lcd";
1178                         resets = <&rcc LTDC_R>;
1179                         status = "disabled";
1180                 };
1181
1182                 iwdg2: watchdog@5a002000 {
1183                         compatible = "st,stm32mp1-iwdg";
1184                         reg = <0x5a002000 0x400>;
1185                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1186                         clock-names = "pclk", "lsi";
1187                         status = "disabled";
1188                 };
1189
1190                 usbphyc: usbphyc@5a006000 {
1191                         #address-cells = <1>;
1192                         #size-cells = <0>;
1193                         compatible = "st,stm32mp1-usbphyc";
1194                         reg = <0x5a006000 0x1000>;
1195                         clocks = <&rcc USBPHY_K>;
1196                         resets = <&rcc USBPHY_R>;
1197                         vdda1v1-supply = <&reg11>;
1198                         vdda1v8-supply = <&reg18>;
1199                         status = "disabled";
1200
1201                         usbphyc_port0: usb-phy@0 {
1202                                 #phy-cells = <0>;
1203                                 reg = <0>;
1204                         };
1205
1206                         usbphyc_port1: usb-phy@1 {
1207                                 #phy-cells = <1>;
1208                                 reg = <1>;
1209                         };
1210                 };
1211
1212                 usart1: serial@5c000000 {
1213                         compatible = "st,stm32h7-uart";
1214                         reg = <0x5c000000 0x400>;
1215                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1216                         clocks = <&rcc USART1_K>;
1217                         status = "disabled";
1218                 };
1219
1220                 spi6: spi@5c001000 {
1221                         #address-cells = <1>;
1222                         #size-cells = <0>;
1223                         compatible = "st,stm32h7-spi";
1224                         reg = <0x5c001000 0x400>;
1225                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1226                         clocks = <&rcc SPI6_K>;
1227                         resets = <&rcc SPI6_R>;
1228                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1229                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1230                         dma-names = "rx", "tx";
1231                         status = "disabled";
1232                 };
1233
1234                 i2c4: i2c@5c002000 {
1235                         compatible = "st,stm32f7-i2c";
1236                         reg = <0x5c002000 0x400>;
1237                         interrupt-names = "event", "error";
1238                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1239                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1240                         clocks = <&rcc I2C4_K>;
1241                         resets = <&rcc I2C4_R>;
1242                         #address-cells = <1>;
1243                         #size-cells = <0>;
1244                         status = "disabled";
1245                 };
1246
1247                 rtc: rtc@5c004000 {
1248                         compatible = "st,stm32mp1-rtc";
1249                         reg = <0x5c004000 0x400>;
1250                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1251                         clock-names = "pclk", "rtc_ck";
1252                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1253                         status = "disabled";
1254                 };
1255
1256                 bsec: nvmem@5c005000 {
1257                         compatible = "st,stm32mp15-bsec";
1258                         reg = <0x5c005000 0x400>;
1259                         #address-cells = <1>;
1260                         #size-cells = <1>;
1261                 };
1262
1263                 i2c6: i2c@5c009000 {
1264                         compatible = "st,stm32f7-i2c";
1265                         reg = <0x5c009000 0x400>;
1266                         interrupt-names = "event", "error";
1267                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1269                         clocks = <&rcc I2C6_K>;
1270                         resets = <&rcc I2C6_R>;
1271                         #address-cells = <1>;
1272                         #size-cells = <0>;
1273                         status = "disabled";
1274                 };
1275         };
1276 };