1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
25 compatible = "arm,cortex-a7";
32 compatible = "arm,psci-1.0";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
42 reg = <0xa0021000 0x1000>,
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
91 thermal-sensors = <&dts>;
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
101 temperature = <120000>;
113 compatible = "syscon-reboot";
120 compatible = "simple-bus";
121 #address-cells = <1>;
123 interrupt-parent = <&intc>;
126 timers2: timer@40000000 {
127 #address-cells = <1>;
129 compatible = "st,stm32-timers";
130 reg = <0x40000000 0x400>;
131 clocks = <&rcc TIM2_K>;
133 dmas = <&dmamux1 18 0x400 0x1>,
134 <&dmamux1 19 0x400 0x1>,
135 <&dmamux1 20 0x400 0x1>,
136 <&dmamux1 21 0x400 0x1>,
137 <&dmamux1 22 0x400 0x1>;
138 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
142 compatible = "st,stm32-pwm";
147 compatible = "st,stm32h7-timer-trigger";
153 timers3: timer@40001000 {
154 #address-cells = <1>;
156 compatible = "st,stm32-timers";
157 reg = <0x40001000 0x400>;
158 clocks = <&rcc TIM3_K>;
160 dmas = <&dmamux1 23 0x400 0x1>,
161 <&dmamux1 24 0x400 0x1>,
162 <&dmamux1 25 0x400 0x1>,
163 <&dmamux1 26 0x400 0x1>,
164 <&dmamux1 27 0x400 0x1>,
165 <&dmamux1 28 0x400 0x1>;
166 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
170 compatible = "st,stm32-pwm";
175 compatible = "st,stm32h7-timer-trigger";
181 timers4: timer@40002000 {
182 #address-cells = <1>;
184 compatible = "st,stm32-timers";
185 reg = <0x40002000 0x400>;
186 clocks = <&rcc TIM4_K>;
188 dmas = <&dmamux1 29 0x400 0x1>,
189 <&dmamux1 30 0x400 0x1>,
190 <&dmamux1 31 0x400 0x1>,
191 <&dmamux1 32 0x400 0x1>;
192 dma-names = "ch1", "ch2", "ch3", "ch4";
196 compatible = "st,stm32-pwm";
201 compatible = "st,stm32h7-timer-trigger";
207 timers5: timer@40003000 {
208 #address-cells = <1>;
210 compatible = "st,stm32-timers";
211 reg = <0x40003000 0x400>;
212 clocks = <&rcc TIM5_K>;
214 dmas = <&dmamux1 55 0x400 0x1>,
215 <&dmamux1 56 0x400 0x1>,
216 <&dmamux1 57 0x400 0x1>,
217 <&dmamux1 58 0x400 0x1>,
218 <&dmamux1 59 0x400 0x1>,
219 <&dmamux1 60 0x400 0x1>;
220 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
224 compatible = "st,stm32-pwm";
229 compatible = "st,stm32h7-timer-trigger";
235 timers6: timer@40004000 {
236 #address-cells = <1>;
238 compatible = "st,stm32-timers";
239 reg = <0x40004000 0x400>;
240 clocks = <&rcc TIM6_K>;
242 dmas = <&dmamux1 69 0x400 0x1>;
247 compatible = "st,stm32h7-timer-trigger";
253 timers7: timer@40005000 {
254 #address-cells = <1>;
256 compatible = "st,stm32-timers";
257 reg = <0x40005000 0x400>;
258 clocks = <&rcc TIM7_K>;
260 dmas = <&dmamux1 70 0x400 0x1>;
265 compatible = "st,stm32h7-timer-trigger";
271 timers12: timer@40006000 {
272 #address-cells = <1>;
274 compatible = "st,stm32-timers";
275 reg = <0x40006000 0x400>;
276 clocks = <&rcc TIM12_K>;
281 compatible = "st,stm32-pwm";
286 compatible = "st,stm32h7-timer-trigger";
292 timers13: timer@40007000 {
293 #address-cells = <1>;
295 compatible = "st,stm32-timers";
296 reg = <0x40007000 0x400>;
297 clocks = <&rcc TIM13_K>;
302 compatible = "st,stm32-pwm";
307 compatible = "st,stm32h7-timer-trigger";
313 timers14: timer@40008000 {
314 #address-cells = <1>;
316 compatible = "st,stm32-timers";
317 reg = <0x40008000 0x400>;
318 clocks = <&rcc TIM14_K>;
323 compatible = "st,stm32-pwm";
328 compatible = "st,stm32h7-timer-trigger";
334 lptimer1: timer@40009000 {
335 #address-cells = <1>;
337 compatible = "st,stm32-lptimer";
338 reg = <0x40009000 0x400>;
339 clocks = <&rcc LPTIM1_K>;
344 compatible = "st,stm32-pwm-lp";
350 compatible = "st,stm32-lptimer-trigger";
356 compatible = "st,stm32-lptimer-counter";
362 #address-cells = <1>;
364 compatible = "st,stm32h7-spi";
365 reg = <0x4000b000 0x400>;
366 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&rcc SPI2_K>;
368 resets = <&rcc SPI2_R>;
369 dmas = <&dmamux1 39 0x400 0x05>,
370 <&dmamux1 40 0x400 0x05>;
371 dma-names = "rx", "tx";
375 i2s2: audio-controller@4000b000 {
376 compatible = "st,stm32h7-i2s";
377 #sound-dai-cells = <0>;
378 reg = <0x4000b000 0x400>;
379 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
380 dmas = <&dmamux1 39 0x400 0x01>,
381 <&dmamux1 40 0x400 0x01>;
382 dma-names = "rx", "tx";
387 #address-cells = <1>;
389 compatible = "st,stm32h7-spi";
390 reg = <0x4000c000 0x400>;
391 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&rcc SPI3_K>;
393 resets = <&rcc SPI3_R>;
394 dmas = <&dmamux1 61 0x400 0x05>,
395 <&dmamux1 62 0x400 0x05>;
396 dma-names = "rx", "tx";
400 i2s3: audio-controller@4000c000 {
401 compatible = "st,stm32h7-i2s";
402 #sound-dai-cells = <0>;
403 reg = <0x4000c000 0x400>;
404 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
405 dmas = <&dmamux1 61 0x400 0x01>,
406 <&dmamux1 62 0x400 0x01>;
407 dma-names = "rx", "tx";
411 spdifrx: audio-controller@4000d000 {
412 compatible = "st,stm32h7-spdifrx";
413 #sound-dai-cells = <0>;
414 reg = <0x4000d000 0x400>;
415 clocks = <&rcc SPDIF_K>;
416 clock-names = "kclk";
417 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
418 dmas = <&dmamux1 93 0x400 0x01>,
419 <&dmamux1 94 0x400 0x01>;
420 dma-names = "rx", "rx-ctrl";
424 usart2: serial@4000e000 {
425 compatible = "st,stm32h7-uart";
426 reg = <0x4000e000 0x400>;
427 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&rcc USART2_K>;
432 usart3: serial@4000f000 {
433 compatible = "st,stm32h7-uart";
434 reg = <0x4000f000 0x400>;
435 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&rcc USART3_K>;
440 uart4: serial@40010000 {
441 compatible = "st,stm32h7-uart";
442 reg = <0x40010000 0x400>;
443 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&rcc UART4_K>;
448 uart5: serial@40011000 {
449 compatible = "st,stm32h7-uart";
450 reg = <0x40011000 0x400>;
451 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&rcc UART5_K>;
457 compatible = "st,stm32f7-i2c";
458 reg = <0x40012000 0x400>;
459 interrupt-names = "event", "error";
460 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&rcc I2C1_K>;
463 resets = <&rcc I2C1_R>;
464 #address-cells = <1>;
470 compatible = "st,stm32f7-i2c";
471 reg = <0x40013000 0x400>;
472 interrupt-names = "event", "error";
473 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&rcc I2C2_K>;
476 resets = <&rcc I2C2_R>;
477 #address-cells = <1>;
483 compatible = "st,stm32f7-i2c";
484 reg = <0x40014000 0x400>;
485 interrupt-names = "event", "error";
486 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&rcc I2C3_K>;
489 resets = <&rcc I2C3_R>;
490 #address-cells = <1>;
496 compatible = "st,stm32f7-i2c";
497 reg = <0x40015000 0x400>;
498 interrupt-names = "event", "error";
499 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&rcc I2C5_K>;
502 resets = <&rcc I2C5_R>;
503 #address-cells = <1>;
509 compatible = "st,stm32-cec";
510 reg = <0x40016000 0x400>;
511 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&rcc CEC_K>, <&clk_lse>;
513 clock-names = "cec", "hdmi-cec";
518 compatible = "st,stm32h7-dac-core";
519 reg = <0x40017000 0x400>;
520 clocks = <&rcc DAC12>;
521 clock-names = "pclk";
522 #address-cells = <1>;
527 compatible = "st,stm32-dac";
528 #io-channels-cells = <1>;
534 compatible = "st,stm32-dac";
535 #io-channels-cells = <1>;
541 uart7: serial@40018000 {
542 compatible = "st,stm32h7-uart";
543 reg = <0x40018000 0x400>;
544 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&rcc UART7_K>;
549 uart8: serial@40019000 {
550 compatible = "st,stm32h7-uart";
551 reg = <0x40019000 0x400>;
552 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&rcc UART8_K>;
557 timers1: timer@44000000 {
558 #address-cells = <1>;
560 compatible = "st,stm32-timers";
561 reg = <0x44000000 0x400>;
562 clocks = <&rcc TIM1_K>;
564 dmas = <&dmamux1 11 0x400 0x1>,
565 <&dmamux1 12 0x400 0x1>,
566 <&dmamux1 13 0x400 0x1>,
567 <&dmamux1 14 0x400 0x1>,
568 <&dmamux1 15 0x400 0x1>,
569 <&dmamux1 16 0x400 0x1>,
570 <&dmamux1 17 0x400 0x1>;
571 dma-names = "ch1", "ch2", "ch3", "ch4",
576 compatible = "st,stm32-pwm";
581 compatible = "st,stm32h7-timer-trigger";
587 timers8: timer@44001000 {
588 #address-cells = <1>;
590 compatible = "st,stm32-timers";
591 reg = <0x44001000 0x400>;
592 clocks = <&rcc TIM8_K>;
594 dmas = <&dmamux1 47 0x400 0x1>,
595 <&dmamux1 48 0x400 0x1>,
596 <&dmamux1 49 0x400 0x1>,
597 <&dmamux1 50 0x400 0x1>,
598 <&dmamux1 51 0x400 0x1>,
599 <&dmamux1 52 0x400 0x1>,
600 <&dmamux1 53 0x400 0x1>;
601 dma-names = "ch1", "ch2", "ch3", "ch4",
606 compatible = "st,stm32-pwm";
611 compatible = "st,stm32h7-timer-trigger";
617 usart6: serial@44003000 {
618 compatible = "st,stm32h7-uart";
619 reg = <0x44003000 0x400>;
620 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&rcc USART6_K>;
626 #address-cells = <1>;
628 compatible = "st,stm32h7-spi";
629 reg = <0x44004000 0x400>;
630 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&rcc SPI1_K>;
632 resets = <&rcc SPI1_R>;
633 dmas = <&dmamux1 37 0x400 0x05>,
634 <&dmamux1 38 0x400 0x05>;
635 dma-names = "rx", "tx";
639 i2s1: audio-controller@44004000 {
640 compatible = "st,stm32h7-i2s";
641 #sound-dai-cells = <0>;
642 reg = <0x44004000 0x400>;
643 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
644 dmas = <&dmamux1 37 0x400 0x01>,
645 <&dmamux1 38 0x400 0x01>;
646 dma-names = "rx", "tx";
651 #address-cells = <1>;
653 compatible = "st,stm32h7-spi";
654 reg = <0x44005000 0x400>;
655 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&rcc SPI4_K>;
657 resets = <&rcc SPI4_R>;
658 dmas = <&dmamux1 83 0x400 0x05>,
659 <&dmamux1 84 0x400 0x05>;
660 dma-names = "rx", "tx";
664 timers15: timer@44006000 {
665 #address-cells = <1>;
667 compatible = "st,stm32-timers";
668 reg = <0x44006000 0x400>;
669 clocks = <&rcc TIM15_K>;
671 dmas = <&dmamux1 105 0x400 0x1>,
672 <&dmamux1 106 0x400 0x1>,
673 <&dmamux1 107 0x400 0x1>,
674 <&dmamux1 108 0x400 0x1>;
675 dma-names = "ch1", "up", "trig", "com";
679 compatible = "st,stm32-pwm";
684 compatible = "st,stm32h7-timer-trigger";
690 timers16: timer@44007000 {
691 #address-cells = <1>;
693 compatible = "st,stm32-timers";
694 reg = <0x44007000 0x400>;
695 clocks = <&rcc TIM16_K>;
697 dmas = <&dmamux1 109 0x400 0x1>,
698 <&dmamux1 110 0x400 0x1>;
699 dma-names = "ch1", "up";
703 compatible = "st,stm32-pwm";
707 compatible = "st,stm32h7-timer-trigger";
713 timers17: timer@44008000 {
714 #address-cells = <1>;
716 compatible = "st,stm32-timers";
717 reg = <0x44008000 0x400>;
718 clocks = <&rcc TIM17_K>;
720 dmas = <&dmamux1 111 0x400 0x1>,
721 <&dmamux1 112 0x400 0x1>;
722 dma-names = "ch1", "up";
726 compatible = "st,stm32-pwm";
731 compatible = "st,stm32h7-timer-trigger";
738 #address-cells = <1>;
740 compatible = "st,stm32h7-spi";
741 reg = <0x44009000 0x400>;
742 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&rcc SPI5_K>;
744 resets = <&rcc SPI5_R>;
745 dmas = <&dmamux1 85 0x400 0x05>,
746 <&dmamux1 86 0x400 0x05>;
747 dma-names = "rx", "tx";
752 compatible = "st,stm32h7-sai";
753 #address-cells = <1>;
755 ranges = <0 0x4400a000 0x400>;
756 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
757 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
758 resets = <&rcc SAI1_R>;
761 sai1a: audio-controller@4400a004 {
762 #sound-dai-cells = <0>;
764 compatible = "st,stm32-sai-sub-a";
766 clocks = <&rcc SAI1_K>;
767 clock-names = "sai_ck";
768 dmas = <&dmamux1 87 0x400 0x01>;
772 sai1b: audio-controller@4400a024 {
773 #sound-dai-cells = <0>;
774 compatible = "st,stm32-sai-sub-b";
776 clocks = <&rcc SAI1_K>;
777 clock-names = "sai_ck";
778 dmas = <&dmamux1 88 0x400 0x01>;
784 compatible = "st,stm32h7-sai";
785 #address-cells = <1>;
787 ranges = <0 0x4400b000 0x400>;
788 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
789 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
790 resets = <&rcc SAI2_R>;
793 sai2a: audio-controller@4400b004 {
794 #sound-dai-cells = <0>;
795 compatible = "st,stm32-sai-sub-a";
797 clocks = <&rcc SAI2_K>;
798 clock-names = "sai_ck";
799 dmas = <&dmamux1 89 0x400 0x01>;
803 sai2b: audio-controller@4400b024 {
804 #sound-dai-cells = <0>;
805 compatible = "st,stm32-sai-sub-b";
807 clocks = <&rcc SAI2_K>;
808 clock-names = "sai_ck";
809 dmas = <&dmamux1 90 0x400 0x01>;
815 compatible = "st,stm32h7-sai";
816 #address-cells = <1>;
818 ranges = <0 0x4400c000 0x400>;
819 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
820 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
821 resets = <&rcc SAI3_R>;
824 sai3a: audio-controller@4400c004 {
825 #sound-dai-cells = <0>;
826 compatible = "st,stm32-sai-sub-a";
828 clocks = <&rcc SAI3_K>;
829 clock-names = "sai_ck";
830 dmas = <&dmamux1 113 0x400 0x01>;
834 sai3b: audio-controller@4400c024 {
835 #sound-dai-cells = <0>;
836 compatible = "st,stm32-sai-sub-b";
838 clocks = <&rcc SAI3_K>;
839 clock-names = "sai_ck";
840 dmas = <&dmamux1 114 0x400 0x01>;
845 dfsdm: dfsdm@4400d000 {
846 compatible = "st,stm32mp1-dfsdm";
847 reg = <0x4400d000 0x800>;
848 clocks = <&rcc DFSDM_K>;
849 clock-names = "dfsdm";
850 #address-cells = <1>;
855 compatible = "st,stm32-dfsdm-adc";
856 #io-channel-cells = <1>;
858 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
859 dmas = <&dmamux1 101 0x400 0x01>;
865 compatible = "st,stm32-dfsdm-adc";
866 #io-channel-cells = <1>;
868 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
869 dmas = <&dmamux1 102 0x400 0x01>;
875 compatible = "st,stm32-dfsdm-adc";
876 #io-channel-cells = <1>;
878 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
879 dmas = <&dmamux1 103 0x400 0x01>;
885 compatible = "st,stm32-dfsdm-adc";
886 #io-channel-cells = <1>;
888 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
889 dmas = <&dmamux1 104 0x400 0x01>;
895 compatible = "st,stm32-dfsdm-adc";
896 #io-channel-cells = <1>;
898 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
899 dmas = <&dmamux1 91 0x400 0x01>;
905 compatible = "st,stm32-dfsdm-adc";
906 #io-channel-cells = <1>;
908 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
909 dmas = <&dmamux1 92 0x400 0x01>;
915 m_can1: can@4400e000 {
916 compatible = "bosch,m_can";
917 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
918 reg-names = "m_can", "message_ram";
919 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
921 interrupt-names = "int0", "int1";
922 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
923 clock-names = "hclk", "cclk";
924 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
928 m_can2: can@4400f000 {
929 compatible = "bosch,m_can";
930 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
931 reg-names = "m_can", "message_ram";
932 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
934 interrupt-names = "int0", "int1";
935 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
936 clock-names = "hclk", "cclk";
937 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
942 compatible = "st,stm32-dma";
943 reg = <0x48000000 0x400>;
944 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&rcc DMA1>;
959 compatible = "st,stm32-dma";
960 reg = <0x48001000 0x400>;
961 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&rcc DMA2>;
975 dmamux1: dma-router@48002000 {
976 compatible = "st,stm32h7-dmamux";
977 reg = <0x48002000 0x1c>;
979 dma-requests = <128>;
980 dma-masters = <&dma1 &dma2>;
982 clocks = <&rcc DMAMUX>;
986 compatible = "st,stm32mp1-adc-core";
987 reg = <0x48003000 0x400>;
988 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
991 clock-names = "bus", "adc";
992 interrupt-controller;
993 #interrupt-cells = <1>;
994 #address-cells = <1>;
999 compatible = "st,stm32mp1-adc";
1000 #io-channel-cells = <1>;
1002 interrupt-parent = <&adc>;
1004 dmas = <&dmamux1 9 0x400 0x01>;
1006 status = "disabled";
1010 compatible = "st,stm32mp1-adc";
1011 #io-channel-cells = <1>;
1013 interrupt-parent = <&adc>;
1015 dmas = <&dmamux1 10 0x400 0x01>;
1017 status = "disabled";
1021 sdmmc3: sdmmc@48004000 {
1022 compatible = "arm,pl18x", "arm,primecell";
1023 arm,primecell-periphid = <0x10153180>;
1024 reg = <0x48004000 0x400>;
1025 reg-names = "sdmmc";
1026 interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
1027 clocks = <&rcc SDMMC3_K>;
1028 clock-names = "apb_pclk";
1029 resets = <&rcc SDMMC3_R>;
1032 max-frequency = <120000000>;
1033 status = "disabled";
1036 usbotg_hs: usb-otg@49000000 {
1037 compatible = "snps,dwc2";
1038 reg = <0x49000000 0x10000>;
1039 clocks = <&rcc USBO_K>;
1040 clock-names = "otg";
1041 resets = <&rcc USBO_R>;
1042 reset-names = "dwc2";
1043 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1044 g-rx-fifo-size = <256>;
1045 g-np-tx-fifo-size = <32>;
1046 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1048 usb33d-supply = <&usb33>;
1049 status = "disabled";
1052 hwspinlock: hwspinlock@4c000000 {
1053 compatible = "st,stm32-hwspinlock";
1054 #hwlock-cells = <1>;
1055 reg = <0x4c000000 0x400>;
1056 clocks = <&rcc HSEM>;
1057 clock-names = "hwspinlock";
1060 ipcc: mailbox@4c001000 {
1061 compatible = "st,stm32mp1-ipcc";
1063 reg = <0x4c001000 0x400>;
1065 interrupts-extended =
1066 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1067 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1069 interrupt-names = "rx", "tx", "wakeup";
1070 clocks = <&rcc IPCC>;
1072 status = "disabled";
1075 dcmi: dcmi@4c006000 {
1076 compatible = "st,stm32-dcmi";
1077 reg = <0x4c006000 0x400>;
1078 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1079 resets = <&rcc CAMITF_R>;
1080 clocks = <&rcc DCMI>;
1081 clock-names = "mclk";
1082 dmas = <&dmamux1 75 0x400 0x0d>;
1084 status = "disabled";
1088 compatible = "st,stm32mp1-rcc", "syscon";
1089 reg = <0x50000000 0x1000>;
1095 compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
1096 reg = <0x50001000 0x400>;
1097 system-power-controller;
1098 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&rcc PLL2_R>;
1101 clock-names = "phyclk";
1104 compatible = "st,stm32mp1,pwr-reg";
1105 st,tzcr = <&rcc 0x0 0x1>;
1108 regulator-name = "reg11";
1109 regulator-min-microvolt = <1100000>;
1110 regulator-max-microvolt = <1100000>;
1114 regulator-name = "reg18";
1115 regulator-min-microvolt = <1800000>;
1116 regulator-max-microvolt = <1800000>;
1120 regulator-name = "usb33";
1121 regulator-min-microvolt = <3300000>;
1122 regulator-max-microvolt = <3300000>;
1127 exti: interrupt-controller@5000d000 {
1128 compatible = "st,stm32mp1-exti", "syscon";
1129 interrupt-controller;
1130 #interrupt-cells = <2>;
1131 reg = <0x5000d000 0x400>;
1134 syscfg: syscon@50020000 {
1135 compatible = "st,stm32mp157-syscfg", "syscon";
1136 reg = <0x50020000 0x400>;
1137 clocks = <&rcc SYSCFG>;
1140 lptimer2: timer@50021000 {
1141 #address-cells = <1>;
1143 compatible = "st,stm32-lptimer";
1144 reg = <0x50021000 0x400>;
1145 clocks = <&rcc LPTIM2_K>;
1146 clock-names = "mux";
1147 status = "disabled";
1150 compatible = "st,stm32-pwm-lp";
1152 status = "disabled";
1156 compatible = "st,stm32-lptimer-trigger";
1158 status = "disabled";
1162 compatible = "st,stm32-lptimer-counter";
1163 status = "disabled";
1167 lptimer3: timer@50022000 {
1168 #address-cells = <1>;
1170 compatible = "st,stm32-lptimer";
1171 reg = <0x50022000 0x400>;
1172 clocks = <&rcc LPTIM3_K>;
1173 clock-names = "mux";
1174 status = "disabled";
1177 compatible = "st,stm32-pwm-lp";
1179 status = "disabled";
1183 compatible = "st,stm32-lptimer-trigger";
1185 status = "disabled";
1189 lptimer4: timer@50023000 {
1190 compatible = "st,stm32-lptimer";
1191 reg = <0x50023000 0x400>;
1192 clocks = <&rcc LPTIM4_K>;
1193 clock-names = "mux";
1194 status = "disabled";
1197 compatible = "st,stm32-pwm-lp";
1199 status = "disabled";
1203 lptimer5: timer@50024000 {
1204 compatible = "st,stm32-lptimer";
1205 reg = <0x50024000 0x400>;
1206 clocks = <&rcc LPTIM5_K>;
1207 clock-names = "mux";
1208 status = "disabled";
1211 compatible = "st,stm32-pwm-lp";
1213 status = "disabled";
1217 vrefbuf: vrefbuf@50025000 {
1218 compatible = "st,stm32-vrefbuf";
1219 reg = <0x50025000 0x8>;
1220 regulator-min-microvolt = <1500000>;
1221 regulator-max-microvolt = <2500000>;
1222 clocks = <&rcc VREF>;
1223 status = "disabled";
1226 sai4: sai@50027000 {
1227 compatible = "st,stm32h7-sai";
1228 #address-cells = <1>;
1230 ranges = <0 0x50027000 0x400>;
1231 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1232 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1233 resets = <&rcc SAI4_R>;
1234 status = "disabled";
1236 sai4a: audio-controller@50027004 {
1237 #sound-dai-cells = <0>;
1238 compatible = "st,stm32-sai-sub-a";
1240 clocks = <&rcc SAI4_K>;
1241 clock-names = "sai_ck";
1242 dmas = <&dmamux1 99 0x400 0x01>;
1243 status = "disabled";
1246 sai4b: audio-controller@50027024 {
1247 #sound-dai-cells = <0>;
1248 compatible = "st,stm32-sai-sub-b";
1250 clocks = <&rcc SAI4_K>;
1251 clock-names = "sai_ck";
1252 dmas = <&dmamux1 100 0x400 0x01>;
1253 status = "disabled";
1257 dts: thermal@50028000 {
1258 compatible = "st,stm32-thermal";
1259 reg = <0x50028000 0x100>;
1260 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&rcc TMPSENS>;
1262 clock-names = "pclk";
1263 #thermal-sensor-cells = <0>;
1264 status = "disabled";
1267 cryp1: cryp@54001000 {
1268 compatible = "st,stm32mp1-cryp";
1269 reg = <0x54001000 0x400>;
1270 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&rcc CRYP1>;
1272 resets = <&rcc CRYP1_R>;
1273 status = "disabled";
1276 hash1: hash@54002000 {
1277 compatible = "st,stm32f756-hash";
1278 reg = <0x54002000 0x400>;
1279 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&rcc HASH1>;
1281 resets = <&rcc HASH1_R>;
1282 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1285 status = "disabled";
1288 rng1: rng@54003000 {
1289 compatible = "st,stm32-rng";
1290 reg = <0x54003000 0x400>;
1291 clocks = <&rcc RNG1_K>;
1292 resets = <&rcc RNG1_R>;
1293 status = "disabled";
1296 mdma1: dma@58000000 {
1297 compatible = "st,stm32h7-mdma";
1298 reg = <0x58000000 0x1000>;
1299 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1300 clocks = <&rcc MDMA>;
1302 dma-channels = <32>;
1303 dma-requests = <48>;
1306 fmc: nand-controller@58002000 {
1307 compatible = "st,stm32mp15-fmc2";
1308 reg = <0x58002000 0x1000>,
1309 <0x80000000 0x1000>,
1310 <0x88010000 0x1000>,
1311 <0x88020000 0x1000>,
1312 <0x81000000 0x1000>,
1313 <0x89010000 0x1000>,
1314 <0x89020000 0x1000>;
1315 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1316 clocks = <&rcc FMC_K>;
1317 resets = <&rcc FMC_R>;
1318 status = "disabled";
1321 qspi: spi@58003000 {
1322 compatible = "st,stm32f469-qspi";
1323 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1324 reg-names = "qspi", "qspi_mm";
1325 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&rcc QSPI_K>;
1327 resets = <&rcc QSPI_R>;
1328 status = "disabled";
1331 sdmmc1: sdmmc@58005000 {
1332 compatible = "arm,pl18x", "arm,primecell";
1333 arm,primecell-periphid = <0x10153180>;
1334 reg = <0x58005000 0x1000>;
1335 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1336 interrupt-names = "cmd_irq";
1337 clocks = <&rcc SDMMC1_K>;
1338 clock-names = "apb_pclk";
1339 resets = <&rcc SDMMC1_R>;
1342 max-frequency = <120000000>;
1345 sdmmc2: sdmmc@58007000 {
1346 compatible = "arm,pl18x", "arm,primecell";
1347 arm,primecell-periphid = <0x10153180>;
1348 reg = <0x58007000 0x1000>;
1349 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
1350 clocks = <&rcc SDMMC2_K>;
1351 clock-names = "apb_pclk";
1352 resets = <&rcc SDMMC2_R>;
1355 max-frequency = <120000000>;
1356 status = "disabled";
1359 crc1: crc@58009000 {
1360 compatible = "st,stm32f7-crc";
1361 reg = <0x58009000 0x400>;
1362 clocks = <&rcc CRC1>;
1363 status = "disabled";
1366 stmmac_axi_config_0: stmmac-axi-config {
1367 snps,wr_osr_lmt = <0x7>;
1368 snps,rd_osr_lmt = <0x7>;
1369 snps,blen = <0 0 0 0 16 8 4>;
1372 ethernet0: ethernet@5800a000 {
1373 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1374 reg = <0x5800a000 0x2000>;
1375 reg-names = "stmmaceth";
1376 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1377 interrupt-names = "macirq";
1378 clock-names = "stmmaceth",
1383 clocks = <&rcc ETHMAC>,
1388 st,syscon = <&syscfg 0x4>;
1391 snps,axi-config = <&stmmac_axi_config_0>;
1393 status = "disabled";
1396 usbh_ohci: usbh-ohci@5800c000 {
1397 compatible = "generic-ohci";
1398 reg = <0x5800c000 0x1000>;
1399 clocks = <&rcc USBH>;
1400 resets = <&rcc USBH_R>;
1401 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1402 status = "disabled";
1405 usbh_ehci: usbh-ehci@5800d000 {
1406 compatible = "generic-ehci";
1407 reg = <0x5800d000 0x1000>;
1408 clocks = <&rcc USBH>;
1409 resets = <&rcc USBH_R>;
1410 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1411 companion = <&usbh_ohci>;
1412 status = "disabled";
1416 compatible = "vivante,gc";
1417 reg = <0x59000000 0x800>;
1418 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&rcc GPU>, <&rcc GPU_K>;
1420 clock-names = "bus" ,"core";
1421 resets = <&rcc GPU_R>;
1422 status = "disabled";
1426 compatible = "st,stm32-dsi";
1427 reg = <0x5a000000 0x800>;
1428 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1429 clock-names = "pclk", "ref", "px_clk";
1430 resets = <&rcc DSI_R>;
1431 reset-names = "apb";
1432 status = "disabled";
1435 ltdc: display-controller@5a001000 {
1436 compatible = "st,stm32-ltdc";
1437 reg = <0x5a001000 0x400>;
1438 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1440 clocks = <&rcc LTDC_PX>;
1441 clock-names = "lcd";
1442 resets = <&rcc LTDC_R>;
1443 status = "disabled";
1446 iwdg2: watchdog@5a002000 {
1447 compatible = "st,stm32mp1-iwdg";
1448 reg = <0x5a002000 0x400>;
1449 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1450 clock-names = "pclk", "lsi";
1451 status = "disabled";
1454 usbphyc: usbphyc@5a006000 {
1455 #address-cells = <1>;
1457 compatible = "st,stm32mp1-usbphyc";
1458 reg = <0x5a006000 0x1000>;
1459 clocks = <&rcc USBPHY_K>;
1460 resets = <&rcc USBPHY_R>;
1461 vdda1v1-supply = <®11>;
1462 vdda1v8-supply = <®18>;
1463 status = "disabled";
1465 usbphyc_port0: usb-phy@0 {
1470 usbphyc_port1: usb-phy@1 {
1476 usart1: serial@5c000000 {
1477 compatible = "st,stm32h7-uart";
1478 reg = <0x5c000000 0x400>;
1479 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1480 clocks = <&rcc USART1_K>;
1481 status = "disabled";
1484 spi6: spi@5c001000 {
1485 #address-cells = <1>;
1487 compatible = "st,stm32h7-spi";
1488 reg = <0x5c001000 0x400>;
1489 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1490 clocks = <&rcc SPI6_K>;
1491 resets = <&rcc SPI6_R>;
1492 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1493 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1494 dma-names = "rx", "tx";
1495 status = "disabled";
1498 i2c4: i2c@5c002000 {
1499 compatible = "st,stm32f7-i2c";
1500 reg = <0x5c002000 0x400>;
1501 interrupt-names = "event", "error";
1502 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1504 clocks = <&rcc I2C4_K>;
1505 resets = <&rcc I2C4_R>;
1506 #address-cells = <1>;
1508 status = "disabled";
1512 compatible = "st,stm32mp1-rtc";
1513 reg = <0x5c004000 0x400>;
1514 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1515 clock-names = "pclk", "rtc_ck";
1516 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1517 status = "disabled";
1520 bsec: nvmem@5c005000 {
1521 compatible = "st,stm32mp15-bsec";
1522 reg = <0x5c005000 0x400>;
1523 #address-cells = <1>;
1533 i2c6: i2c@5c009000 {
1534 compatible = "st,stm32f7-i2c";
1535 reg = <0x5c009000 0x400>;
1536 interrupt-names = "event", "error";
1537 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1539 clocks = <&rcc I2C6_K>;
1540 resets = <&rcc I2C6_R>;
1541 #address-cells = <1>;
1543 status = "disabled";
1548 compatible = "simple-bus";
1549 #address-cells = <1>;
1551 dma-ranges = <0x00000000 0x38000000 0x10000>,
1552 <0x10000000 0x10000000 0x60000>,
1553 <0x30000000 0x30000000 0x60000>;
1555 m4_rproc: m4@10000000 {
1556 compatible = "st,stm32mp1-m4";
1557 reg = <0x10000000 0x40000>,
1558 <0x30000000 0x40000>,
1559 <0x38000000 0x10000>;
1560 resets = <&rcc MCU_R>;
1561 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1562 st,syscfg-tz = <&rcc 0x000 0x1>;
1563 status = "disabled";