1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
25 compatible = "arm,cortex-a7";
32 compatible = "arm,psci";
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
60 intc: interrupt-controller@a0021000 {
61 compatible = "arm,cortex-a7-gic";
62 #interrupt-cells = <3>;
64 reg = <0xa0021000 0x1000>,
69 compatible = "arm,armv7-timer";
70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 interrupt-parent = <&intc>;
80 compatible = "fixed-clock";
81 clock-frequency = <24000000>;
86 compatible = "fixed-clock";
87 clock-frequency = <64000000>;
92 compatible = "fixed-clock";
93 clock-frequency = <32768>;
98 compatible = "fixed-clock";
99 clock-frequency = <32000>;
104 compatible = "fixed-clock";
105 clock-frequency = <4000000>;
110 #address-cells = <1>;
112 compatible = "st,stm32mp157c-pd";
114 pd_core_ret: core-ret-power-domain@1 {
115 #address-cells = <1>;
118 #power-domain-cells = <0>;
119 label = "CORE-RETENTION";
121 pd_core: core-power-domain@2 {
123 #power-domain-cells = <0>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
133 interrupt-parent = <&intc>;
136 timers2: timer@40000000 {
137 #address-cells = <1>;
139 compatible = "st,stm32-timers";
140 reg = <0x40000000 0x400>;
141 clocks = <&rcc TIM2_K>;
146 compatible = "st,stm32-pwm";
151 compatible = "st,stm32h7-timer-trigger";
157 timers3: timer@40001000 {
158 #address-cells = <1>;
160 compatible = "st,stm32-timers";
161 reg = <0x40001000 0x400>;
162 clocks = <&rcc TIM3_K>;
167 compatible = "st,stm32-pwm";
172 compatible = "st,stm32h7-timer-trigger";
178 timers4: timer@40002000 {
179 #address-cells = <1>;
181 compatible = "st,stm32-timers";
182 reg = <0x40002000 0x400>;
183 clocks = <&rcc TIM4_K>;
188 compatible = "st,stm32-pwm";
193 compatible = "st,stm32h7-timer-trigger";
199 timers5: timer@40003000 {
200 #address-cells = <1>;
202 compatible = "st,stm32-timers";
203 reg = <0x40003000 0x400>;
204 clocks = <&rcc TIM5_K>;
209 compatible = "st,stm32-pwm";
214 compatible = "st,stm32h7-timer-trigger";
220 timers6: timer@40004000 {
221 #address-cells = <1>;
223 compatible = "st,stm32-timers";
224 reg = <0x40004000 0x400>;
225 clocks = <&rcc TIM6_K>;
230 compatible = "st,stm32h7-timer-trigger";
236 timers7: timer@40005000 {
237 #address-cells = <1>;
239 compatible = "st,stm32-timers";
240 reg = <0x40005000 0x400>;
241 clocks = <&rcc TIM7_K>;
246 compatible = "st,stm32h7-timer-trigger";
252 timers12: timer@40006000 {
253 #address-cells = <1>;
255 compatible = "st,stm32-timers";
256 reg = <0x40006000 0x400>;
257 clocks = <&rcc TIM12_K>;
262 compatible = "st,stm32-pwm";
267 compatible = "st,stm32h7-timer-trigger";
273 timers13: timer@40007000 {
274 #address-cells = <1>;
276 compatible = "st,stm32-timers";
277 reg = <0x40007000 0x400>;
278 clocks = <&rcc TIM13_K>;
283 compatible = "st,stm32-pwm";
288 compatible = "st,stm32h7-timer-trigger";
294 timers14: timer@40008000 {
295 #address-cells = <1>;
297 compatible = "st,stm32-timers";
298 reg = <0x40008000 0x400>;
299 clocks = <&rcc TIM14_K>;
304 compatible = "st,stm32-pwm";
309 compatible = "st,stm32h7-timer-trigger";
315 lptimer1: timer@40009000 {
316 #address-cells = <1>;
318 compatible = "st,stm32-lptimer";
319 reg = <0x40009000 0x400>;
320 clocks = <&rcc LPTIM1_K>;
325 compatible = "st,stm32-pwm-lp";
331 compatible = "st,stm32-lptimer-trigger";
337 compatible = "st,stm32-lptimer-counter";
342 usart2: serial@4000e000 {
343 compatible = "st,stm32h7-uart";
344 reg = <0x4000e000 0x400>;
345 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&rcc USART2_K>;
350 usart3: serial@4000f000 {
351 compatible = "st,stm32h7-uart";
352 reg = <0x4000f000 0x400>;
353 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&rcc USART3_K>;
358 uart4: serial@40010000 {
359 compatible = "st,stm32h7-uart";
360 reg = <0x40010000 0x400>;
361 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&rcc UART4_K>;
366 uart5: serial@40011000 {
367 compatible = "st,stm32h7-uart";
368 reg = <0x40011000 0x400>;
369 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&rcc UART5_K>;
375 compatible = "st,stm32f7-i2c";
376 reg = <0x40012000 0x400>;
377 interrupt-names = "event", "error";
378 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&rcc I2C1_K>;
381 resets = <&rcc I2C1_R>;
382 #address-cells = <1>;
388 compatible = "st,stm32f7-i2c";
389 reg = <0x40013000 0x400>;
390 interrupt-names = "event", "error";
391 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&rcc I2C2_K>;
394 resets = <&rcc I2C2_R>;
395 #address-cells = <1>;
401 compatible = "st,stm32f7-i2c";
402 reg = <0x40014000 0x400>;
403 interrupt-names = "event", "error";
404 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&rcc I2C3_K>;
407 resets = <&rcc I2C3_R>;
408 #address-cells = <1>;
414 compatible = "st,stm32f7-i2c";
415 reg = <0x40015000 0x400>;
416 interrupt-names = "event", "error";
417 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&rcc I2C5_K>;
420 resets = <&rcc I2C5_R>;
421 #address-cells = <1>;
427 compatible = "st,stm32-cec";
428 reg = <0x40016000 0x400>;
429 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&rcc CEC_K>, <&clk_lse>;
431 clock-names = "cec", "hdmi-cec";
436 compatible = "st,stm32h7-dac-core";
437 reg = <0x40017000 0x400>;
438 clocks = <&rcc DAC12>;
439 clock-names = "pclk";
440 #address-cells = <1>;
445 compatible = "st,stm32-dac";
446 #io-channels-cells = <1>;
452 compatible = "st,stm32-dac";
453 #io-channels-cells = <1>;
459 uart7: serial@40018000 {
460 compatible = "st,stm32h7-uart";
461 reg = <0x40018000 0x400>;
462 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&rcc UART7_K>;
467 uart8: serial@40019000 {
468 compatible = "st,stm32h7-uart";
469 reg = <0x40019000 0x400>;
470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&rcc UART8_K>;
475 timers1: timer@44000000 {
476 #address-cells = <1>;
478 compatible = "st,stm32-timers";
479 reg = <0x44000000 0x400>;
480 clocks = <&rcc TIM1_K>;
485 compatible = "st,stm32-pwm";
490 compatible = "st,stm32h7-timer-trigger";
496 timers8: timer@44001000 {
497 #address-cells = <1>;
499 compatible = "st,stm32-timers";
500 reg = <0x44001000 0x400>;
501 clocks = <&rcc TIM8_K>;
506 compatible = "st,stm32-pwm";
511 compatible = "st,stm32h7-timer-trigger";
517 usart6: serial@44003000 {
518 compatible = "st,stm32h7-uart";
519 reg = <0x44003000 0x400>;
520 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&rcc USART6_K>;
525 timers15: timer@44006000 {
526 #address-cells = <1>;
528 compatible = "st,stm32-timers";
529 reg = <0x44006000 0x400>;
530 clocks = <&rcc TIM15_K>;
535 compatible = "st,stm32-pwm";
540 compatible = "st,stm32h7-timer-trigger";
546 timers16: timer@44007000 {
547 #address-cells = <1>;
549 compatible = "st,stm32-timers";
550 reg = <0x44007000 0x400>;
551 clocks = <&rcc TIM16_K>;
556 compatible = "st,stm32-pwm";
560 compatible = "st,stm32h7-timer-trigger";
566 timers17: timer@44008000 {
567 #address-cells = <1>;
569 compatible = "st,stm32-timers";
570 reg = <0x44008000 0x400>;
571 clocks = <&rcc TIM17_K>;
576 compatible = "st,stm32-pwm";
581 compatible = "st,stm32h7-timer-trigger";
588 compatible = "st,stm32-dma";
589 reg = <0x48000000 0x400>;
590 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&rcc DMA1>;
605 compatible = "st,stm32-dma";
606 reg = <0x48001000 0x400>;
607 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&rcc DMA2>;
621 dmamux1: dma-router@48002000 {
622 compatible = "st,stm32h7-dmamux";
623 reg = <0x48002000 0x1c>;
625 dma-requests = <128>;
626 dma-masters = <&dma1 &dma2>;
628 clocks = <&rcc DMAMUX>;
632 compatible = "st,stm32mp1-adc-core";
633 reg = <0x48003000 0x400>;
634 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
637 clock-names = "bus", "adc";
638 interrupt-controller;
639 #interrupt-cells = <1>;
640 #address-cells = <1>;
645 compatible = "st,stm32mp1-adc";
646 #io-channel-cells = <1>;
648 interrupt-parent = <&adc>;
654 compatible = "st,stm32mp1-adc";
655 #io-channel-cells = <1>;
657 interrupt-parent = <&adc>;
663 sdmmc3: sdmmc@48004000 {
664 compatible = "st,stm32-sdmmc2";
665 reg = <0x48004000 0x400>, <0x48005000 0x400>;
666 reg-names = "sdmmc", "delay";
667 interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>;
668 clocks = <&rcc SDMMC3_K>;
669 resets = <&rcc SDMMC3_R>;
673 max-frequency = <120000000>;
677 usbotg_hs: usb-otg@49000000 {
678 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
679 reg = <0x49000000 0x10000>;
680 clocks = <&rcc USBO_K>;
682 resets = <&rcc USBO_R>;
683 reset-names = "dwc2";
684 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
685 g-rx-fifo-size = <256>;
686 g-np-tx-fifo-size = <32>;
687 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
689 power-domains = <&pd_core>;
694 compatible = "st,stm32mp1-rcc", "syscon";
695 reg = <0x50000000 0x1000>;
700 rcc_reboot: rcc-reboot@50000000 {
701 compatible = "syscon-reboot";
708 compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
709 reg = <0x50001000 0x400>;
710 system-power-controller;
711 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&rcc PLL2_R>;
714 clock-names = "phyclk";
717 compatible = "st,stm32mp1,pwr-reg";
718 st,tzcr = <&rcc 0x0 0x1>;
721 regulator-name = "reg11";
722 regulator-min-microvolt = <1100000>;
723 regulator-max-microvolt = <1100000>;
727 regulator-name = "reg18";
728 regulator-min-microvolt = <1800000>;
729 regulator-max-microvolt = <1800000>;
733 regulator-name = "usb33";
734 regulator-min-microvolt = <3300000>;
735 regulator-max-microvolt = <3300000>;
740 exti: interrupt-controller@5000d000 {
741 compatible = "st,stm32mp1-exti", "syscon";
742 interrupt-controller;
743 #interrupt-cells = <2>;
744 reg = <0x5000d000 0x400>;
747 syscfg: system-config@50020000 {
748 compatible = "st,stm32-syscfg", "syscon";
749 reg = <0x50020000 0x400>;
752 lptimer2: timer@50021000 {
753 #address-cells = <1>;
755 compatible = "st,stm32-lptimer";
756 reg = <0x50021000 0x400>;
757 clocks = <&rcc LPTIM2_K>;
762 compatible = "st,stm32-pwm-lp";
768 compatible = "st,stm32-lptimer-trigger";
774 compatible = "st,stm32-lptimer-counter";
779 lptimer3: timer@50022000 {
780 #address-cells = <1>;
782 compatible = "st,stm32-lptimer";
783 reg = <0x50022000 0x400>;
784 clocks = <&rcc LPTIM3_K>;
789 compatible = "st,stm32-pwm-lp";
795 compatible = "st,stm32-lptimer-trigger";
801 lptimer4: timer@50023000 {
802 compatible = "st,stm32-lptimer";
803 reg = <0x50023000 0x400>;
804 clocks = <&rcc LPTIM4_K>;
809 compatible = "st,stm32-pwm-lp";
815 lptimer5: timer@50024000 {
816 compatible = "st,stm32-lptimer";
817 reg = <0x50024000 0x400>;
818 clocks = <&rcc LPTIM5_K>;
823 compatible = "st,stm32-pwm-lp";
829 vrefbuf: vrefbuf@50025000 {
830 compatible = "st,stm32-vrefbuf";
831 reg = <0x50025000 0x8>;
832 regulator-min-microvolt = <1500000>;
833 regulator-max-microvolt = <2500000>;
834 clocks = <&rcc VREF>;
838 cryp1: cryp@54001000 {
839 compatible = "st,stm32mp1-cryp";
840 reg = <0x54001000 0x400>;
841 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&rcc CRYP1>;
843 resets = <&rcc CRYP1_R>;
848 compatible = "st,stm32-rng";
849 reg = <0x54003000 0x400>;
850 clocks = <&rcc RNG1_K>;
851 resets = <&rcc RNG1_R>;
855 mdma1: dma@58000000 {
856 compatible = "st,stm32h7-mdma";
857 reg = <0x58000000 0x1000>;
858 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&rcc MDMA>;
865 qspi: qspi@58003000 {
866 compatible = "st,stm32f469-qspi";
867 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
868 reg-names = "qspi", "qspi_mm";
869 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
870 clocks = <&rcc QSPI_K>;
871 resets = <&rcc QSPI_R>;
875 sdmmc1: sdmmc@58005000 {
876 compatible = "st,stm32-sdmmc2";
877 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
878 reg-names = "sdmmc", "delay";
879 clocks = <&rcc SDMMC1_K>;
880 resets = <&rcc SDMMC1_R>;
884 max-frequency = <120000000>;
888 sdmmc2: sdmmc@58007000 {
889 compatible = "st,stm32-sdmmc2";
890 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
891 reg-names = "sdmmc", "delay";
892 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
893 clocks = <&rcc SDMMC2_K>;
894 resets = <&rcc SDMMC2_R>;
898 max-frequency = <120000000>;
903 compatible = "st,stm32f7-crc";
904 reg = <0x58009000 0x400>;
905 clocks = <&rcc CRC1>;
909 usbh_ohci: usbh-ohci@5800c000 {
910 compatible = "generic-ohci";
911 reg = <0x5800c000 0x1000>;
912 clocks = <&rcc USBH>;
913 resets = <&rcc USBH_R>;
914 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
918 usbh_ehci: usbh-ehci@5800d000 {
919 compatible = "generic-ehci";
920 reg = <0x5800d000 0x1000>;
921 clocks = <&rcc USBH>;
922 resets = <&rcc USBH_R>;
923 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
924 companion = <&usbh_ohci>;
929 compatible = "st,stm32-dsi";
930 reg = <0x5a000000 0x800>;
931 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
932 clock-names = "pclk", "ref", "px_clk";
933 resets = <&rcc DSI_R>;
938 ltdc: display-controller@5a001000 {
939 compatible = "st,stm32-ltdc";
940 reg = <0x5a001000 0x400>;
941 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&rcc LTDC_PX>;
945 resets = <&rcc LTDC_R>;
949 usbphyc: usbphyc@5a006000 {
950 #address-cells = <1>;
952 compatible = "st,stm32mp1-usbphyc";
953 reg = <0x5a006000 0x1000>;
954 clocks = <&rcc USBPHY_K>;
955 resets = <&rcc USBPHY_R>;
958 usbphyc_port0: usb-phy@0 {
963 usbphyc_port1: usb-phy@1 {
969 usart1: serial@5c000000 {
970 compatible = "st,stm32h7-uart";
971 reg = <0x5c000000 0x400>;
972 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&rcc USART1_K>;
978 compatible = "st,stm32f7-i2c";
979 reg = <0x5c002000 0x400>;
980 interrupt-names = "event", "error";
981 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&rcc I2C4_K>;
984 resets = <&rcc I2C4_R>;
985 #address-cells = <1>;
991 compatible = "st,stm32f7-i2c";
992 reg = <0x5c009000 0x400>;
993 interrupt-names = "event", "error";
994 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&rcc I2C6_K>;
997 resets = <&rcc I2C6_R>;
998 #address-cells = <1>;
1000 status = "disabled";