arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp157-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 mmc0 = &sdmmc1;
  13                 mmc1 = &sdmmc2;
  14                 i2c3 = &i2c4;
  15         };
  16
  17         config {
  18                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  19                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  20         };
  21
  22         led {
  23                 compatible = "gpio-leds";
  24
  25                 red {
  26                         label = "stm32mp:red:status";
  27                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  28                         default-state = "off";
  29                 };
  30                 green {
  31                         label = "stm32mp:green:user";
  32                         gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  33                         default-state = "on";
  34                 };
  35                 orange {
  36                         label = "stm32mp:orange:status";
  37                         gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
  38                         default-state = "off";
  39                 };
  40                 blue {
  41                         label = "stm32mp:blue:user";
  42                         gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
  43                 };
  44         };
  45 };
  46
  47 &clk_hse {
  48         st,digbypass;
  49 };
  50
  51 &uart4_pins_a {
  52         u-boot,dm-pre-reloc;
  53         pins1 {
  54                 u-boot,dm-pre-reloc;
  55         };
  56         pins2 {
  57                 u-boot,dm-pre-reloc;
  58         };
  59 };
  60
  61 &i2c4_pins_a {
  62         u-boot,dm-pre-reloc;
  63         pins {
  64                 u-boot,dm-pre-reloc;
  65         };
  66 };
  67
  68 &uart4 {
  69         u-boot,dm-pre-reloc;
  70 };
  71
  72 &i2c4 {
  73         u-boot,dm-pre-reloc;
  74 };
  75
  76 &pmic {
  77         u-boot,dm-pre-reloc;
  78 };
  79
  80 &rcc {
  81         st,clksrc = <
  82                 CLK_MPU_PLL1P
  83                 CLK_AXI_PLL2P
  84                 CLK_MCU_PLL3P
  85                 CLK_PLL12_HSE
  86                 CLK_PLL3_HSE
  87                 CLK_PLL4_HSE
  88                 CLK_RTC_LSE
  89                 CLK_MCO1_DISABLED
  90                 CLK_MCO2_DISABLED
  91         >;
  92
  93         st,clkdiv = <
  94                 1 /*MPU*/
  95                 0 /*AXI*/
  96                 0 /*MCU*/
  97                 1 /*APB1*/
  98                 1 /*APB2*/
  99                 1 /*APB3*/
 100                 1 /*APB4*/
 101                 2 /*APB5*/
 102                 23 /*RTC*/
 103                 0 /*MCO1*/
 104                 0 /*MCO2*/
 105         >;
 106
 107         st,pkcs = <
 108                 CLK_CKPER_HSE
 109                 CLK_FMC_ACLK
 110                 CLK_QSPI_ACLK
 111                 CLK_ETH_DISABLED
 112                 CLK_SDMMC12_PLL4P
 113                 CLK_DSI_DSIPLL
 114                 CLK_STGEN_HSE
 115                 CLK_USBPHY_HSE
 116                 CLK_SPI2S1_PLL3Q
 117                 CLK_SPI2S23_PLL3Q
 118                 CLK_SPI45_HSI
 119                 CLK_SPI6_HSI
 120                 CLK_I2C46_HSI
 121                 CLK_SDMMC3_PLL4P
 122                 CLK_USBO_USBPHY
 123                 CLK_ADC_CKPER
 124                 CLK_CEC_LSE
 125                 CLK_I2C12_HSI
 126                 CLK_I2C35_HSI
 127                 CLK_UART1_HSI
 128                 CLK_UART24_HSI
 129                 CLK_UART35_HSI
 130                 CLK_UART6_HSI
 131                 CLK_UART78_HSI
 132                 CLK_SPDIF_PLL4P
 133                 CLK_FDCAN_PLL4Q
 134                 CLK_SAI1_PLL3Q
 135                 CLK_SAI2_PLL3Q
 136                 CLK_SAI3_PLL3Q
 137                 CLK_SAI4_PLL3Q
 138                 CLK_RNG1_LSI
 139                 CLK_RNG2_LSI
 140                 CLK_LPTIM1_PCLK1
 141                 CLK_LPTIM23_PCLK3
 142                 CLK_LPTIM45_LSE
 143         >;
 144
 145         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 146         pll1: st,pll@0 {
 147                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 148                 frac = < 0x800 >;
 149                 u-boot,dm-pre-reloc;
 150         };
 151
 152         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 153         pll2: st,pll@1 {
 154                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 155                 frac = < 0x1400 >;
 156                 u-boot,dm-pre-reloc;
 157         };
 158
 159         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 160         pll3: st,pll@2 {
 161                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 162                 frac = < 0x1a04 >;
 163                 u-boot,dm-pre-reloc;
 164         };
 165
 166         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 167         pll4: st,pll@3 {
 168                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 169                 u-boot,dm-pre-reloc;
 170         };
 171 };
 172
 173 /* SPL part **************************************/
 174 /* MMC1 boot */
 175 &sdmmc1_b4_pins_a {
 176         u-boot,dm-spl;
 177         pins {
 178                 u-boot,dm-spl;
 179         };
 180 };
 181
 182 &sdmmc1_dir_pins_a {
 183         u-boot,dm-spl;
 184         pins {
 185                 u-boot,dm-spl;
 186         };
 187 };
 188
 189 &sdmmc1 {
 190         u-boot,dm-spl;
 191 };
 192
 193 /* MMC2 boot */
 194 &sdmmc2_b4_pins_a {
 195         u-boot,dm-spl;
 196         pins {
 197                 u-boot,dm-spl;
 198         };
 199 };
 200
 201 &sdmmc2_d47_pins_a {
 202         u-boot,dm-spl;
 203         pins {
 204                 u-boot,dm-spl;
 205         };
 206 };
 207
 208 &sdmmc2 {
 209         u-boot,dm-spl;
 210 };