arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp157-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14                 mmc1 = &sdmmc2;
  15         };
  16
  17         config {
  18                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  19                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  20         };
  21
  22         led {
  23                 compatible = "gpio-leds";
  24
  25                 red {
  26                         label = "stm32mp:red:status";
  27                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  28                         default-state = "off";
  29                 };
  30                 green {
  31                         label = "stm32mp:green:user";
  32                         gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  33                         default-state = "on";
  34                 };
  35                 orange {
  36                         label = "stm32mp:orange:status";
  37                         gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
  38                         default-state = "off";
  39                 };
  40                 blue {
  41                         label = "stm32mp:blue:user";
  42                         gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
  43                 };
  44         };
  45 };
  46
  47 &clk_hse {
  48         st,digbypass;
  49 };
  50
  51 &i2c4 {
  52         u-boot,dm-pre-reloc;
  53 };
  54
  55 &i2c4_pins_a {
  56         u-boot,dm-pre-reloc;
  57         pins {
  58                 u-boot,dm-pre-reloc;
  59         };
  60 };
  61
  62 &pmic {
  63         u-boot,dm-pre-reloc;
  64 };
  65
  66 &rcc {
  67         st,clksrc = <
  68                 CLK_MPU_PLL1P
  69                 CLK_AXI_PLL2P
  70                 CLK_MCU_PLL3P
  71                 CLK_PLL12_HSE
  72                 CLK_PLL3_HSE
  73                 CLK_PLL4_HSE
  74                 CLK_RTC_LSE
  75                 CLK_MCO1_DISABLED
  76                 CLK_MCO2_DISABLED
  77         >;
  78
  79         st,clkdiv = <
  80                 1 /*MPU*/
  81                 0 /*AXI*/
  82                 0 /*MCU*/
  83                 1 /*APB1*/
  84                 1 /*APB2*/
  85                 1 /*APB3*/
  86                 1 /*APB4*/
  87                 2 /*APB5*/
  88                 23 /*RTC*/
  89                 0 /*MCO1*/
  90                 0 /*MCO2*/
  91         >;
  92
  93         st,pkcs = <
  94                 CLK_CKPER_HSE
  95                 CLK_FMC_ACLK
  96                 CLK_QSPI_ACLK
  97                 CLK_ETH_DISABLED
  98                 CLK_SDMMC12_PLL4P
  99                 CLK_DSI_DSIPLL
 100                 CLK_STGEN_HSE
 101                 CLK_USBPHY_HSE
 102                 CLK_SPI2S1_PLL3Q
 103                 CLK_SPI2S23_PLL3Q
 104                 CLK_SPI45_HSI
 105                 CLK_SPI6_HSI
 106                 CLK_I2C46_HSI
 107                 CLK_SDMMC3_PLL4P
 108                 CLK_USBO_USBPHY
 109                 CLK_ADC_CKPER
 110                 CLK_CEC_LSE
 111                 CLK_I2C12_HSI
 112                 CLK_I2C35_HSI
 113                 CLK_UART1_HSI
 114                 CLK_UART24_HSI
 115                 CLK_UART35_HSI
 116                 CLK_UART6_HSI
 117                 CLK_UART78_HSI
 118                 CLK_SPDIF_PLL4P
 119                 CLK_FDCAN_PLL4Q
 120                 CLK_SAI1_PLL3Q
 121                 CLK_SAI2_PLL3Q
 122                 CLK_SAI3_PLL3Q
 123                 CLK_SAI4_PLL3Q
 124                 CLK_RNG1_LSI
 125                 CLK_RNG2_LSI
 126                 CLK_LPTIM1_PCLK1
 127                 CLK_LPTIM23_PCLK3
 128                 CLK_LPTIM45_LSE
 129         >;
 130
 131         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 132         pll1: st,pll@0 {
 133                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 134                 frac = < 0x800 >;
 135                 u-boot,dm-pre-reloc;
 136         };
 137
 138         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 139         pll2: st,pll@1 {
 140                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 141                 frac = < 0x1400 >;
 142                 u-boot,dm-pre-reloc;
 143         };
 144
 145         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 146         pll3: st,pll@2 {
 147                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 148                 frac = < 0x1a04 >;
 149                 u-boot,dm-pre-reloc;
 150         };
 151
 152         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 153         pll4: st,pll@3 {
 154                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 155                 u-boot,dm-pre-reloc;
 156         };
 157 };
 158
 159 &sdmmc1 {
 160         u-boot,dm-spl;
 161 };
 162
 163 &sdmmc1_b4_pins_a {
 164         u-boot,dm-spl;
 165         pins {
 166                 u-boot,dm-spl;
 167         };
 168 };
 169
 170 &sdmmc1_dir_pins_a {
 171         u-boot,dm-spl;
 172         pins1 {
 173                 u-boot,dm-spl;
 174         };
 175         pins2 {
 176                 u-boot,dm-spl;
 177         };
 178 };
 179
 180 &sdmmc2 {
 181         u-boot,dm-spl;
 182 };
 183
 184 &sdmmc2_b4_pins_a {
 185         u-boot,dm-spl;
 186         pins {
 187                 u-boot,dm-spl;
 188         };
 189 };
 190
 191 &sdmmc2_d47_pins_a {
 192         u-boot,dm-spl;
 193         pins {
 194                 u-boot,dm-spl;
 195         };
 196 };
 197
 198 &uart4 {
 199         u-boot,dm-pre-reloc;
 200 };
 201
 202 &uart4_pins_a {
 203         u-boot,dm-pre-reloc;
 204         pins1 {
 205                 u-boot,dm-pre-reloc;
 206         };
 207         pins2 {
 208                 u-boot,dm-pre-reloc;
 209         };
 210 };