arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp157-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 mmc0 = &sdmmc1;
  13                 mmc1 = &sdmmc2;
  14                 i2c3 = &i2c4;
  15         };
  16
  17         led {
  18                 compatible = "gpio-leds";
  19
  20                 red {
  21                         label = "stm32mp:red:status";
  22                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  23                         default-state = "off";
  24                 };
  25                 green {
  26                         label = "stm32mp:green:user";
  27                         gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  28                         default-state = "on";
  29                 };
  30                 orange {
  31                         label = "stm32mp:orange:status";
  32                         gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>;
  33                         default-state = "off";
  34                 };
  35                 blue {
  36                         label = "stm32mp:blue:user";
  37                         gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
  38                 };
  39         };
  40 };
  41
  42 &uart4_pins_a {
  43         u-boot,dm-pre-reloc;
  44         pins1 {
  45                 u-boot,dm-pre-reloc;
  46         };
  47         pins2 {
  48                 u-boot,dm-pre-reloc;
  49         };
  50 };
  51
  52 &i2c4_pins_a {
  53         u-boot,dm-pre-reloc;
  54         pins {
  55                 u-boot,dm-pre-reloc;
  56         };
  57 };
  58
  59 &uart4 {
  60         u-boot,dm-pre-reloc;
  61 };
  62
  63 &i2c4 {
  64         u-boot,dm-pre-reloc;
  65 };
  66
  67 &pmic {
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 /* CLOCK init */
  72 &rcc {
  73         st,clksrc = <
  74                 CLK_MPU_PLL1P
  75                 CLK_AXI_PLL2P
  76                 CLK_MCU_PLL3P
  77                 CLK_PLL12_HSE
  78                 CLK_PLL3_HSE
  79                 CLK_PLL4_HSE
  80                 CLK_RTC_LSE
  81                 CLK_MCO1_DISABLED
  82                 CLK_MCO2_DISABLED
  83         >;
  84
  85         st,clkdiv = <
  86                 1 /*MPU*/
  87                 0 /*AXI*/
  88                 0 /*MCU*/
  89                 1 /*APB1*/
  90                 1 /*APB2*/
  91                 1 /*APB3*/
  92                 1 /*APB4*/
  93                 2 /*APB5*/
  94                 23 /*RTC*/
  95                 0 /*MCO1*/
  96                 0 /*MCO2*/
  97         >;
  98
  99         st,pkcs = <
 100                 CLK_CKPER_HSE
 101                 CLK_FMC_ACLK
 102                 CLK_QSPI_ACLK
 103                 CLK_ETH_DISABLED
 104                 CLK_SDMMC12_PLL3R
 105                 CLK_DSI_DSIPLL
 106                 CLK_STGEN_HSE
 107                 CLK_USBPHY_HSE
 108                 CLK_SPI2S1_PLL3Q
 109                 CLK_SPI2S23_PLL3Q
 110                 CLK_SPI45_HSI
 111                 CLK_SPI6_HSI
 112                 CLK_I2C46_HSI
 113                 CLK_SDMMC3_PLL3R
 114                 CLK_USBO_USBPHY
 115                 CLK_ADC_CKPER
 116                 CLK_CEC_LSE
 117                 CLK_I2C12_HSI
 118                 CLK_I2C35_HSI
 119                 CLK_UART1_HSI
 120                 CLK_UART24_HSI
 121                 CLK_UART35_HSI
 122                 CLK_UART6_HSI
 123                 CLK_UART78_HSI
 124                 CLK_SPDIF_PLL3Q
 125                 CLK_FDCAN_PLL4Q
 126                 CLK_SAI1_PLL3Q
 127                 CLK_SAI2_PLL3Q
 128                 CLK_SAI3_PLL3Q
 129                 CLK_SAI4_PLL3Q
 130                 CLK_RNG1_CSI
 131                 CLK_RNG2_CSI
 132                 CLK_LPTIM1_PCLK1
 133                 CLK_LPTIM23_PCLK3
 134                 CLK_LPTIM45_PCLK3
 135         >;
 136
 137         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 138         pll1: st,pll@0 {
 139                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 140                 frac = < 0x800 >;
 141                 u-boot,dm-pre-reloc;
 142         };
 143
 144         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 145         pll2: st,pll@1 {
 146                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 147                 frac = < 0x1400 >;
 148                 u-boot,dm-pre-reloc;
 149         };
 150
 151         /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */
 152         pll3: st,pll@2 {
 153                 cfg = < 2 97 3 15 7 PQR(1,1,1) >;
 154                 frac = < 0x9ba >;
 155                 u-boot,dm-pre-reloc;
 156         };
 157
 158         /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
 159         pll4: st,pll@3 {
 160                 cfg = < 5 126 8 8 8 PQR(1,1,1) >;
 161                 u-boot,dm-pre-reloc;
 162         };
 163 };
 164
 165 /* SPL part **************************************/
 166 /* MMC1 boot */
 167 &sdmmc1_b4_pins_a {
 168         u-boot,dm-spl;
 169         pins {
 170                 u-boot,dm-spl;
 171         };
 172 };
 173
 174 &sdmmc1_dir_pins_a {
 175         u-boot,dm-spl;
 176         pins {
 177                 u-boot,dm-spl;
 178         };
 179 };
 180
 181 &sdmmc1 {
 182         u-boot,dm-spl;
 183 };
 184
 185 /* MMC2 boot */
 186 &sdmmc2_b4_pins_a {
 187         u-boot,dm-spl;
 188         pins {
 189                 u-boot,dm-spl;
 190         };
 191 };
 192
 193 &sdmmc2_d47_pins_a {
 194         u-boot,dm-spl;
 195         pins {
 196                 u-boot,dm-spl;
 197         };
 198 };
 199
 200 &sdmmc2 {
 201         u-boot,dm-spl;
 202 };