arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 #include <dt-bindings/clock/stm32mp1-clksrc.h>
   7 #include "stm32mp157-u-boot.dtsi"
   8 #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
   9
  10 / {
  11         aliases {
  12                 i2c3 = &i2c4;
  13                 mmc0 = &sdmmc1;
  14                 usb0 = &usbotg_hs;
  15         };
  16         config {
  17                 u-boot,boot-led = "heartbeat";
  18                 u-boot,error-led = "error";
  19                 st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
  20                 st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  21                 st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
  22         };
  23         led {
  24                 red {
  25                         label = "error";
  26                         gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  27                         default-state = "off";
  28                         status = "okay";
  29                 };
  30
  31                 blue {
  32                         default-state = "on";
  33                 };
  34         };
  35 };
  36
  37 &adc {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&adc12_usb_pwr_pins_a>;
  40         vdd-supply = <&vdd>;
  41         vdda-supply = <&vdd>;
  42         vref-supply = <&vrefbuf>;
  43         status = "okay";
  44         adc1: adc@0 {
  45                 /*
  46                  * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
  47                  * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
  48                  * 5 * (56 + 47kOhms) * 5pF => 2.5us.
  49                  * Use arbitrary margin here (e.g. 5µs).
  50                  */
  51                 st,min-sample-time-nsecs = <5000>;
  52                 /* ANA0, ANA1, USB Type-C CC1 & CC2 */
  53                 st,adc-channels = <0 1 18 19>;
  54                 status = "okay";
  55         };
  56 };
  57
  58 &clk_hse {
  59         st,digbypass;
  60 };
  61
  62 &i2c4 {
  63         u-boot,dm-pre-reloc;
  64 };
  65
  66 &i2c4_pins_a {
  67         u-boot,dm-pre-reloc;
  68         pins {
  69                 u-boot,dm-pre-reloc;
  70         };
  71 };
  72
  73 &pmic {
  74         u-boot,dm-pre-reloc;
  75 };
  76
  77 &rcc {
  78         st,clksrc = <
  79                 CLK_MPU_PLL1P
  80                 CLK_AXI_PLL2P
  81                 CLK_MCU_PLL3P
  82                 CLK_PLL12_HSE
  83                 CLK_PLL3_HSE
  84                 CLK_PLL4_HSE
  85                 CLK_RTC_LSE
  86                 CLK_MCO1_DISABLED
  87                 CLK_MCO2_DISABLED
  88         >;
  89
  90         st,clkdiv = <
  91                 1 /*MPU*/
  92                 0 /*AXI*/
  93                 0 /*MCU*/
  94                 1 /*APB1*/
  95                 1 /*APB2*/
  96                 1 /*APB3*/
  97                 1 /*APB4*/
  98                 2 /*APB5*/
  99                 23 /*RTC*/
 100                 0 /*MCO1*/
 101                 0 /*MCO2*/
 102         >;
 103
 104         st,pkcs = <
 105                 CLK_CKPER_HSE
 106                 CLK_FMC_ACLK
 107                 CLK_QSPI_ACLK
 108                 CLK_ETH_DISABLED
 109                 CLK_SDMMC12_PLL4P
 110                 CLK_DSI_DSIPLL
 111                 CLK_STGEN_HSE
 112                 CLK_USBPHY_HSE
 113                 CLK_SPI2S1_PLL3Q
 114                 CLK_SPI2S23_PLL3Q
 115                 CLK_SPI45_HSI
 116                 CLK_SPI6_HSI
 117                 CLK_I2C46_HSI
 118                 CLK_SDMMC3_PLL4P
 119                 CLK_USBO_USBPHY
 120                 CLK_ADC_CKPER
 121                 CLK_CEC_LSE
 122                 CLK_I2C12_HSI
 123                 CLK_I2C35_HSI
 124                 CLK_UART1_HSI
 125                 CLK_UART24_HSI
 126                 CLK_UART35_HSI
 127                 CLK_UART6_HSI
 128                 CLK_UART78_HSI
 129                 CLK_SPDIF_PLL4P
 130                 CLK_FDCAN_PLL4Q
 131                 CLK_SAI1_PLL3Q
 132                 CLK_SAI2_PLL3Q
 133                 CLK_SAI3_PLL3Q
 134                 CLK_SAI4_PLL3Q
 135                 CLK_RNG1_LSI
 136                 CLK_RNG2_LSI
 137                 CLK_LPTIM1_PCLK1
 138                 CLK_LPTIM23_PCLK3
 139                 CLK_LPTIM45_LSE
 140         >;
 141
 142         /* VCO = 1300.0 MHz => P = 650 (CPU) */
 143         pll1: st,pll@0 {
 144                 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 145                 frac = < 0x800 >;
 146                 u-boot,dm-pre-reloc;
 147         };
 148
 149         /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 150         pll2: st,pll@1 {
 151                 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
 152                 frac = < 0x1400 >;
 153                 u-boot,dm-pre-reloc;
 154         };
 155
 156         /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 157         pll3: st,pll@2 {
 158                 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
 159                 frac = < 0x1a04 >;
 160                 u-boot,dm-pre-reloc;
 161         };
 162
 163         /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 164         pll4: st,pll@3 {
 165                 cfg = < 3 98 5 7 7 PQR(1,1,1) >;
 166                 u-boot,dm-pre-reloc;
 167         };
 168 };
 169
 170 &sdmmc1 {
 171         u-boot,dm-spl;
 172 };
 173
 174 &sdmmc1_b4_pins_a {
 175         u-boot,dm-spl;
 176         pins {
 177                 u-boot,dm-spl;
 178         };
 179 };
 180
 181 &uart4 {
 182         u-boot,dm-pre-reloc;
 183 };
 184
 185 &uart4_pins_a {
 186         u-boot,dm-pre-reloc;
 187         pins1 {
 188                 u-boot,dm-pre-reloc;
 189         };
 190         pins2 {
 191                 u-boot,dm-pre-reloc;
 192         };
 193 };
 194
 195 &usbotg_hs {
 196         u-boot,force-b-session-valid;
 197         hnp-srp-disable;
 198 };