arch/arm/dts/stm32mp157.dtsi

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
   2 /*
   3  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset-controller/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         aliases {
  32                 serial3 = &uart4;
  33         };
  34
  35         intc: interrupt-controller@a0021000 {
  36                 compatible = "arm,cortex-a7-gic";
  37                 #interrupt-cells = <3>;
  38                 interrupt-controller;
  39                 reg = <0xa0021000 0x1000>,
  40                       <0xa0022000 0x2000>;
  41         };
  42
  43         clocks {
  44                 clk_hse: clk-hse {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <24000000>;
  48                 };
  49
  50                 clk_hsi: clk-hsi {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <64000000>;
  54                 };
  55
  56                 clk_lse: clk-lse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 clk_lsi: clk-lsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32000>;
  66                 };
  67
  68                 clk_csi: clk-csi {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <4000000>;
  72                 };
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 interrupt-parent = <&intc>;
  80                 ranges;
  81
  82                 uart4: serial@40010000 {
  83                         compatible = "st,stm32h7-uart";
  84                         reg = <0x40010000 0x400>;
  85                         clocks = <&rcc_clk UART4_K>;
  86                         status = "disabled";
  87                 };
  88
  89                 rcc: rcc@50000000 {
  90                         compatible = "syscon", "simple-mfd";
  91
  92                         reg = <0x50000000 0x1000>;
  93
  94                         rcc_clk: rcc-clk@50000000 {
  95                                 #clock-cells = <1>;
  96                                 compatible = "st,stm32mp1-rcc-clk";
  97                         };
  98
  99                         rcc_rst: rcc-reset@50000000 {
 100                                 #reset-cells = <1>;
 101                                 compatible = "st,stm32mp1-rcc-rst";
 102                         };
 103                 };
 104
 105                 pinctrl: pin-controller {
 106                         compatible = "st,stm32mp157-pinctrl";
 107                         #address-cells = <1>;
 108                         #size-cells = <1>;
 109                         ranges = <0 0x50002000 0xa400>;
 110                         pins-are-numbered;
 111
 112                         gpioa: gpio@50002000 {
 113                                 gpio-controller;
 114                                 #gpio-cells = <2>;
 115                                 interrupt-controller;
 116                                 #interrupt-cells = <2>;
 117                                 reg = <0x0 0x400>;
 118                                 clocks = <&rcc_clk GPIOA>;
 119                                 st,bank-name = "GPIOA";
 120                                 ngpios = <16>;
 121                                 gpio-ranges = <&pinctrl 0 0 16>;
 122                                 status = "disabled";
 123                         };
 124
 125                         gpiob: gpio@50003000 {
 126                                 gpio-controller;
 127                                 #gpio-cells = <2>;
 128                                 interrupt-controller;
 129                                 #interrupt-cells = <2>;
 130                                 reg = <0x1000 0x400>;
 131                                 clocks = <&rcc_clk GPIOB>;
 132                                 st,bank-name = "GPIOB";
 133                                 ngpios = <16>;
 134                                 gpio-ranges = <&pinctrl 0 16 16>;
 135                                 status = "disabled";
 136                         };
 137
 138                         gpioc: gpio@50004000 {
 139                                 gpio-controller;
 140                                 #gpio-cells = <2>;
 141                                 interrupt-controller;
 142                                 #interrupt-cells = <2>;
 143                                 reg = <0x2000 0x400>;
 144                                 clocks = <&rcc_clk GPIOC>;
 145                                 st,bank-name = "GPIOC";
 146                                 ngpios = <16>;
 147                                 gpio-ranges = <&pinctrl 0 32 16>;
 148                                 status = "disabled";
 149                         };
 150
 151                         gpiod: gpio@50005000 {
 152                                 gpio-controller;
 153                                 #gpio-cells = <2>;
 154                                 interrupt-controller;
 155                                 #interrupt-cells = <2>;
 156                                 reg = <0x3000 0x400>;
 157                                 clocks = <&rcc_clk GPIOD>;
 158                                 st,bank-name = "GPIOD";
 159                                 ngpios = <16>;
 160                                 gpio-ranges = <&pinctrl 0 48 16>;
 161                                 status = "disabled";
 162                         };
 163
 164                         gpioe: gpio@50006000 {
 165                                 gpio-controller;
 166                                 #gpio-cells = <2>;
 167                                 interrupt-controller;
 168                                 #interrupt-cells = <2>;
 169                                 reg = <0x4000 0x400>;
 170                                 clocks = <&rcc_clk GPIOE>;
 171                                 st,bank-name = "GPIOE";
 172                                 ngpios = <16>;
 173                                 gpio-ranges = <&pinctrl 0 64 16>;
 174                                 status = "disabled";
 175                         };
 176
 177                         gpiof: gpio@50007000 {
 178                                 gpio-controller;
 179                                 #gpio-cells = <2>;
 180                                 interrupt-controller;
 181                                 #interrupt-cells = <2>;
 182                                 reg = <0x5000 0x400>;
 183                                 clocks = <&rcc_clk GPIOF>;
 184                                 st,bank-name = "GPIOF";
 185                                 ngpios = <16>;
 186                                 gpio-ranges = <&pinctrl 0 80 16>;
 187                                 status = "disabled";
 188                         };
 189
 190                         gpiog: gpio@50008000 {
 191                                 gpio-controller;
 192                                 #gpio-cells = <2>;
 193                                 interrupt-controller;
 194                                 #interrupt-cells = <2>;
 195                                 reg = <0x6000 0x400>;
 196                                 clocks = <&rcc_clk GPIOG>;
 197                                 st,bank-name = "GPIOG";
 198                                 ngpios = <16>;
 199                                 gpio-ranges = <&pinctrl 0 96 16>;
 200                                 status = "disabled";
 201                         };
 202
 203                         gpioh: gpio@50009000 {
 204                                 gpio-controller;
 205                                 #gpio-cells = <2>;
 206                                 interrupt-controller;
 207                                 #interrupt-cells = <2>;
 208                                 reg = <0x7000 0x400>;
 209                                 clocks = <&rcc_clk GPIOH>;
 210                                 st,bank-name = "GPIOH";
 211                                 ngpios = <16>;
 212                                 gpio-ranges = <&pinctrl 0 112 16>;
 213                                 status = "disabled";
 214                         };
 215
 216                         gpioi: gpio@5000a000 {
 217                                 gpio-controller;
 218                                 #gpio-cells = <2>;
 219                                 interrupt-controller;
 220                                 #interrupt-cells = <2>;
 221                                 reg = <0x8000 0x400>;
 222                                 clocks = <&rcc_clk GPIOI>;
 223                                 st,bank-name = "GPIOI";
 224                                 ngpios = <16>;
 225                                 gpio-ranges = <&pinctrl 0 128 16>;
 226                                 status = "disabled";
 227                         };
 228
 229                         gpioj: gpio@5000b000 {
 230                                 gpio-controller;
 231                                 #gpio-cells = <2>;
 232                                 interrupt-controller;
 233                                 #interrupt-cells = <2>;
 234                                 reg = <0x9000 0x400>;
 235                                 clocks = <&rcc_clk GPIOJ>;
 236                                 st,bank-name = "GPIOJ";
 237                                 ngpios = <16>;
 238                                 gpio-ranges = <&pinctrl 0 144 16>;
 239                                 status = "disabled";
 240                         };
 241
 242                         gpiok: gpio@5000c000 {
 243                                 gpio-controller;
 244                                 #gpio-cells = <2>;
 245                                 interrupt-controller;
 246                                 #interrupt-cells = <2>;
 247                                 reg = <0xa000 0x400>;
 248                                 clocks = <&rcc_clk GPIOK>;
 249                                 st,bank-name = "GPIOK";
 250                                 ngpios = <8>;
 251                                 gpio-ranges = <&pinctrl 0 160 8>;
 252                                 status = "disabled";
 253                         };
 254                 };
 255
 256                 pinctrl_z: pin-controller-z {
 257                         compatible = "st,stm32mp157-z-pinctrl";
 258                         #address-cells = <1>;
 259                         #size-cells = <1>;
 260                         ranges = <0 0x54004000 0x400>;
 261                         pins-are-numbered;
 262
 263                         gpioz: gpio@54004000 {
 264                                 gpio-controller;
 265                                 #gpio-cells = <2>;
 266                                 interrupt-controller;
 267                                 #interrupt-cells = <2>;
 268                                 reg = <0 0x400>;
 269                                 clocks = <&rcc_clk GPIOZ>;
 270                                 st,bank-name = "GPIOZ";
 271                                 st,bank-ioport = <11>;
 272                                 ngpios = <8>;
 273                                 gpio-ranges = <&pinctrl_z 0 400 8>;
 274                                 status = "disabled";
 275                         };
 276                 };
 277
 278                 sdmmc1: sdmmc@58005000 {
 279                         compatible = "st,stm32-sdmmc2";
 280                         reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
 281                         reg-names = "sdmmc", "delay";
 282                         clocks = <&rcc_clk SDMMC1_K>;
 283                         resets = <&rcc_rst SDMMC1_R>;
 284                         st,idma = <1>;
 285                         cap-sd-highspeed;
 286                         cap-mmc-highspeed;
 287                         max-frequency = <120000000>;
 288                         status = "disabled";
 289                 };
 290
 291                 i2c4: i2c@5c002000 {
 292                         compatible = "st,stm32f7-i2c";
 293                         reg = <0x5c002000 0x400>;
 294                         interrupt-names = "event", "error", "wakeup";
 295                         clocks = <&rcc_clk I2C4_K>;
 296                         resets = <&rcc_rst I2C4_R>;
 297                         #address-cells = <1>;
 298                         #size-cells = <0>;
 299                         wakeup-source;
 300                         status = "disabled";
 301                 };
 302         };
 303 };