1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
19 gpioa: gpio@50002000 {
23 #interrupt-cells = <2>;
25 clocks = <&rcc GPIOA>;
26 st,bank-name = "GPIOA";
28 gpio-ranges = <&pinctrl 0 0 16>;
31 gpiob: gpio@50003000 {
35 #interrupt-cells = <2>;
37 clocks = <&rcc GPIOB>;
38 st,bank-name = "GPIOB";
40 gpio-ranges = <&pinctrl 0 16 16>;
43 gpioc: gpio@50004000 {
47 #interrupt-cells = <2>;
49 clocks = <&rcc GPIOC>;
50 st,bank-name = "GPIOC";
52 gpio-ranges = <&pinctrl 0 32 16>;
55 gpiod: gpio@50005000 {
59 #interrupt-cells = <2>;
61 clocks = <&rcc GPIOD>;
62 st,bank-name = "GPIOD";
64 gpio-ranges = <&pinctrl 0 48 16>;
67 gpioe: gpio@50006000 {
71 #interrupt-cells = <2>;
73 clocks = <&rcc GPIOE>;
74 st,bank-name = "GPIOE";
76 gpio-ranges = <&pinctrl 0 64 16>;
79 gpiof: gpio@50007000 {
83 #interrupt-cells = <2>;
85 clocks = <&rcc GPIOF>;
86 st,bank-name = "GPIOF";
88 gpio-ranges = <&pinctrl 0 80 16>;
91 gpiog: gpio@50008000 {
95 #interrupt-cells = <2>;
97 clocks = <&rcc GPIOG>;
98 st,bank-name = "GPIOG";
100 gpio-ranges = <&pinctrl 0 96 16>;
103 gpioh: gpio@50009000 {
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 reg = <0x7000 0x400>;
109 clocks = <&rcc GPIOH>;
110 st,bank-name = "GPIOH";
112 gpio-ranges = <&pinctrl 0 112 16>;
115 gpioi: gpio@5000a000 {
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 reg = <0x8000 0x400>;
121 clocks = <&rcc GPIOI>;
122 st,bank-name = "GPIOI";
124 gpio-ranges = <&pinctrl 0 128 16>;
127 gpioj: gpio@5000b000 {
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 reg = <0x9000 0x400>;
133 clocks = <&rcc GPIOJ>;
134 st,bank-name = "GPIOJ";
136 gpio-ranges = <&pinctrl 0 144 16>;
139 gpiok: gpio@5000c000 {
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 reg = <0xa000 0x400>;
145 clocks = <&rcc GPIOK>;
146 st,bank-name = "GPIOK";
148 gpio-ranges = <&pinctrl 0 160 8>;
153 pinmux = <STM32_PINMUX('A', 15, AF4)>;
160 i2c1_pins_a: i2c1-0 {
162 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
163 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
170 i2c2_pins_a: i2c2-0 {
172 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
173 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
180 i2c5_pins_a: i2c5-0 {
182 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
183 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
190 pwm2_pins_a: pwm2-0 {
192 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
199 pwm8_pins_a: pwm8-0 {
201 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
208 pwm12_pins_a: pwm12-0 {
210 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
217 qspi_clk_pins_a: qspi-clk-0 {
219 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
226 qspi_bk1_pins_a: qspi-bk1-0 {
228 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
229 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
230 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
231 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
237 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
244 qspi_bk2_pins_a: qspi-bk2-0 {
246 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
247 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
248 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
249 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
255 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
261 sdmmc1_b4_pins_a: sdmmc1-b4@0 {
263 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
264 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
265 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
266 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
267 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
268 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
275 sdmmc1_dir_pins_a: sdmmc1-dir@0 {
277 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
278 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
279 <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
280 <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
286 sdmmc2_b4_pins_a: sdmmc2-b4@0 {
288 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
289 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
290 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
291 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
292 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
293 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
300 sdmmc2_d47_pins_a: sdmmc2-d47@0 {
302 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
303 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
304 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
305 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
312 uart4_pins_a: uart4-0 {
314 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
320 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
326 pinctrl_z: pin-controller-z@54004000 {
327 #address-cells = <1>;
329 compatible = "st,stm32mp157-z-pinctrl";
330 ranges = <0 0x54004000 0x400>;
332 interrupt-parent = <&exti>;
333 st,syscfg = <&exti 0x60 0xff>;
335 gpioz: gpio@54004000 {
338 interrupt-controller;
339 #interrupt-cells = <2>;
341 clocks = <&rcc GPIOZ>;
342 st,bank-name = "GPIOZ";
343 st,bank-ioport = <11>;
345 gpio-ranges = <&pinctrl_z 0 400 8>;
348 i2c4_pins_a: i2c4-0 {
350 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
351 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */