1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
19 gpioa: gpio@50002000 {
23 #interrupt-cells = <2>;
25 clocks = <&rcc GPIOA>;
26 st,bank-name = "GPIOA";
28 gpio-ranges = <&pinctrl 0 0 16>;
31 gpiob: gpio@50003000 {
35 #interrupt-cells = <2>;
37 clocks = <&rcc GPIOB>;
38 st,bank-name = "GPIOB";
40 gpio-ranges = <&pinctrl 0 16 16>;
43 gpioc: gpio@50004000 {
47 #interrupt-cells = <2>;
49 clocks = <&rcc GPIOC>;
50 st,bank-name = "GPIOC";
52 gpio-ranges = <&pinctrl 0 32 16>;
55 gpiod: gpio@50005000 {
59 #interrupt-cells = <2>;
61 clocks = <&rcc GPIOD>;
62 st,bank-name = "GPIOD";
64 gpio-ranges = <&pinctrl 0 48 16>;
67 gpioe: gpio@50006000 {
71 #interrupt-cells = <2>;
73 clocks = <&rcc GPIOE>;
74 st,bank-name = "GPIOE";
76 gpio-ranges = <&pinctrl 0 64 16>;
79 gpiof: gpio@50007000 {
83 #interrupt-cells = <2>;
85 clocks = <&rcc GPIOF>;
86 st,bank-name = "GPIOF";
88 gpio-ranges = <&pinctrl 0 80 16>;
91 gpiog: gpio@50008000 {
95 #interrupt-cells = <2>;
97 clocks = <&rcc GPIOG>;
98 st,bank-name = "GPIOG";
100 gpio-ranges = <&pinctrl 0 96 16>;
103 gpioh: gpio@50009000 {
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 reg = <0x7000 0x400>;
109 clocks = <&rcc GPIOH>;
110 st,bank-name = "GPIOH";
112 gpio-ranges = <&pinctrl 0 112 16>;
115 gpioi: gpio@5000a000 {
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 reg = <0x8000 0x400>;
121 clocks = <&rcc GPIOI>;
122 st,bank-name = "GPIOI";
124 gpio-ranges = <&pinctrl 0 128 16>;
127 gpioj: gpio@5000b000 {
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 reg = <0x9000 0x400>;
133 clocks = <&rcc GPIOJ>;
134 st,bank-name = "GPIOJ";
136 gpio-ranges = <&pinctrl 0 144 16>;
139 gpiok: gpio@5000c000 {
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 reg = <0xa000 0x400>;
145 clocks = <&rcc GPIOK>;
146 st,bank-name = "GPIOK";
148 gpio-ranges = <&pinctrl 0 160 8>;
151 adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
153 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
154 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
160 pinmux = <STM32_PINMUX('A', 15, AF4)>;
167 ethernet0_rgmii_pins_a: rgmii-0 {
169 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
170 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
171 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
172 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
173 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
174 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
175 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
176 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
182 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
188 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
189 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
190 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
191 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
192 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
193 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
198 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
200 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
201 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
202 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
203 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
204 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
205 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
206 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
207 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
208 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
209 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
210 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
211 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
212 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
213 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
214 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
220 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
221 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
222 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
223 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
224 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
225 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
226 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
227 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
228 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
229 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
230 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
231 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
232 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
238 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
243 fmc_sleep_pins_a: fmc-sleep-0 {
245 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
246 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
247 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
248 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
249 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
250 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
251 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
252 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
253 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
254 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
255 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
256 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
257 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
258 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
262 i2c1_pins_a: i2c1-0 {
264 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
265 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
272 i2c1_pins_b: i2c1-1 {
274 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
275 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
282 i2c2_pins_a: i2c2-0 {
284 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
285 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
292 i2c2_pins_b: i2c2-1 {
294 pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */
295 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
302 i2c5_pins_a: i2c5-0 {
304 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
305 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
312 m_can1_pins_a: m-can1-0 {
314 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
320 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
325 pwm2_pins_a: pwm2-0 {
327 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
334 pwm8_pins_a: pwm8-0 {
336 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
343 pwm12_pins_a: pwm12-0 {
345 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
352 qspi_clk_pins_a: qspi-clk-0 {
354 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
361 qspi_bk1_pins_a: qspi-bk1-0 {
363 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
364 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
365 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
366 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
372 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
379 qspi_bk2_pins_a: qspi-bk2-0 {
381 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
382 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
383 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
384 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
390 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
396 sdmmc1_b4_pins_a: sdmmc1-b4@0 {
398 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
399 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
400 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
401 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
402 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
403 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
410 sdmmc1_dir_pins_a: sdmmc1-dir@0 {
412 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
413 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
414 <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
415 <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
421 sdmmc2_b4_pins_a: sdmmc2-b4@0 {
423 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
424 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
425 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
426 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
427 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
428 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
435 sdmmc2_d47_pins_a: sdmmc2-d47@0 {
437 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
438 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
439 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
440 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
447 spi2_pins_a: spi2-0 {
449 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
450 <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
451 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
457 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
462 stusb1600_pins_a: stusb1600-0 {
464 pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
469 uart4_pins_a: uart4-0 {
471 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
477 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
482 uart4_pins_b: uart4-1 {
484 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
490 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
495 uart7_pins_a: uart7-0 {
497 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
503 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
504 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
505 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
510 usbotg_hs_pins_a: usbotg_hs-0 {
512 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
517 pinctrl_z: pin-controller-z@54004000 {
518 #address-cells = <1>;
520 compatible = "st,stm32mp157-z-pinctrl";
521 ranges = <0 0x54004000 0x400>;
523 interrupt-parent = <&exti>;
524 st,syscfg = <&exti 0x60 0xff>;
526 gpioz: gpio@54004000 {
529 interrupt-controller;
530 #interrupt-cells = <2>;
532 clocks = <&rcc GPIOZ>;
533 st,bank-name = "GPIOZ";
534 st,bank-ioport = <11>;
536 gpio-ranges = <&pinctrl_z 0 400 8>;
539 i2c4_pins_a: i2c4-0 {
541 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
542 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
549 spi1_pins_a: spi1-0 {
551 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
552 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
559 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */