1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
19 gpioa: gpio@50002000 {
23 #interrupt-cells = <2>;
25 clocks = <&rcc GPIOA>;
26 st,bank-name = "GPIOA";
28 gpio-ranges = <&pinctrl 0 0 16>;
31 gpiob: gpio@50003000 {
35 #interrupt-cells = <2>;
37 clocks = <&rcc GPIOB>;
38 st,bank-name = "GPIOB";
40 gpio-ranges = <&pinctrl 0 16 16>;
43 gpioc: gpio@50004000 {
47 #interrupt-cells = <2>;
49 clocks = <&rcc GPIOC>;
50 st,bank-name = "GPIOC";
52 gpio-ranges = <&pinctrl 0 32 16>;
55 gpiod: gpio@50005000 {
59 #interrupt-cells = <2>;
61 clocks = <&rcc GPIOD>;
62 st,bank-name = "GPIOD";
64 gpio-ranges = <&pinctrl 0 48 16>;
67 gpioe: gpio@50006000 {
71 #interrupt-cells = <2>;
73 clocks = <&rcc GPIOE>;
74 st,bank-name = "GPIOE";
76 gpio-ranges = <&pinctrl 0 64 16>;
79 gpiof: gpio@50007000 {
83 #interrupt-cells = <2>;
85 clocks = <&rcc GPIOF>;
86 st,bank-name = "GPIOF";
88 gpio-ranges = <&pinctrl 0 80 16>;
91 gpiog: gpio@50008000 {
95 #interrupt-cells = <2>;
97 clocks = <&rcc GPIOG>;
98 st,bank-name = "GPIOG";
100 gpio-ranges = <&pinctrl 0 96 16>;
103 gpioh: gpio@50009000 {
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 reg = <0x7000 0x400>;
109 clocks = <&rcc GPIOH>;
110 st,bank-name = "GPIOH";
112 gpio-ranges = <&pinctrl 0 112 16>;
115 gpioi: gpio@5000a000 {
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 reg = <0x8000 0x400>;
121 clocks = <&rcc GPIOI>;
122 st,bank-name = "GPIOI";
124 gpio-ranges = <&pinctrl 0 128 16>;
127 gpioj: gpio@5000b000 {
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 reg = <0x9000 0x400>;
133 clocks = <&rcc GPIOJ>;
134 st,bank-name = "GPIOJ";
136 gpio-ranges = <&pinctrl 0 144 16>;
139 gpiok: gpio@5000c000 {
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 reg = <0xa000 0x400>;
145 clocks = <&rcc GPIOK>;
146 st,bank-name = "GPIOK";
148 gpio-ranges = <&pinctrl 0 160 8>;
151 adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
153 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
154 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
160 pinmux = <STM32_PINMUX('A', 15, AF4)>;
167 ethernet0_rgmii_pins_a: rgmii-0 {
169 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
170 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
171 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
172 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
173 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
174 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
175 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
176 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
177 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
183 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
184 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
185 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
186 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
187 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
188 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
193 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
195 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
196 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
197 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
198 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
199 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
200 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
201 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
202 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
203 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
204 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
205 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
206 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
207 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
208 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
209 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
213 i2c1_pins_a: i2c1-0 {
215 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
216 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
223 i2c2_pins_a: i2c2-0 {
225 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
226 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
233 i2c5_pins_a: i2c5-0 {
235 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
236 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
243 m_can1_pins_a: m-can1-0 {
245 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
251 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
256 pwm2_pins_a: pwm2-0 {
258 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
265 pwm8_pins_a: pwm8-0 {
267 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
274 pwm12_pins_a: pwm12-0 {
276 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
283 qspi_clk_pins_a: qspi-clk-0 {
285 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
292 qspi_bk1_pins_a: qspi-bk1-0 {
294 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
295 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
296 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
297 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
303 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
310 qspi_bk2_pins_a: qspi-bk2-0 {
312 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
313 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
314 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
315 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
321 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
327 sdmmc1_b4_pins_a: sdmmc1-b4@0 {
329 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
330 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
331 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
332 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
333 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
334 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
341 sdmmc1_dir_pins_a: sdmmc1-dir@0 {
343 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
344 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
345 <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
346 <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
352 sdmmc2_b4_pins_a: sdmmc2-b4@0 {
354 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
355 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
356 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
357 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
358 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
359 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
366 sdmmc2_d47_pins_a: sdmmc2-d47@0 {
368 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
369 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
370 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
371 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
378 stusb1600_pins_a: stusb1600-0 {
380 pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
385 uart4_pins_a: uart4-0 {
387 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
393 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
398 usbotg_hs_pins_a: usbotg_hs-0 {
400 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
405 pinctrl_z: pin-controller-z@54004000 {
406 #address-cells = <1>;
408 compatible = "st,stm32mp157-z-pinctrl";
409 ranges = <0 0x54004000 0x400>;
411 interrupt-parent = <&exti>;
412 st,syscfg = <&exti 0x60 0xff>;
414 gpioz: gpio@54004000 {
417 interrupt-controller;
418 #interrupt-cells = <2>;
420 clocks = <&rcc GPIOZ>;
421 st,bank-name = "GPIOZ";
422 st,bank-ioport = <11>;
424 gpio-ranges = <&pinctrl_z 0 400 8>;
427 i2c4_pins_a: i2c4-0 {
429 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
430 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
437 spi1_pins_a: spi1-0 {
439 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
440 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
447 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */