1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
26 compatible = "arm,psci-1.0";
28 cpu_off = <0x84000002>;
29 cpu_on = <0x84000003>;
32 intc: interrupt-controller@a0021000 {
33 compatible = "arm,cortex-a7-gic";
34 #interrupt-cells = <3>;
36 reg = <0xa0021000 0x1000>,
41 compatible = "arm,armv7-timer";
42 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
46 interrupt-parent = <&intc>;
52 compatible = "fixed-clock";
53 clock-frequency = <24000000>;
58 compatible = "fixed-clock";
59 clock-frequency = <64000000>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
70 compatible = "fixed-clock";
71 clock-frequency = <32000>;
76 compatible = "fixed-clock";
77 clock-frequency = <4000000>;
82 cpu_thermal: cpu-thermal {
83 polling-delay-passive = <0>;
85 thermal-sensors = <&dts>;
88 cpu_alert1: cpu-alert1 {
89 temperature = <85000>;
95 temperature = <120000>;
106 booster: regulator-booster {
107 compatible = "st,stm32mp1-booster";
108 st,syscfg = <&syscfg>;
113 compatible = "syscon-reboot";
120 compatible = "simple-bus";
121 #address-cells = <1>;
123 interrupt-parent = <&intc>;
126 timers2: timer@40000000 {
127 #address-cells = <1>;
129 compatible = "st,stm32-timers";
130 reg = <0x40000000 0x400>;
131 clocks = <&rcc TIM2_K>;
133 dmas = <&dmamux1 18 0x400 0x1>,
134 <&dmamux1 19 0x400 0x1>,
135 <&dmamux1 20 0x400 0x1>,
136 <&dmamux1 21 0x400 0x1>,
137 <&dmamux1 22 0x400 0x1>;
138 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
142 compatible = "st,stm32-pwm";
148 compatible = "st,stm32h7-timer-trigger";
154 compatible = "st,stm32-timer-counter";
159 timers3: timer@40001000 {
160 #address-cells = <1>;
162 compatible = "st,stm32-timers";
163 reg = <0x40001000 0x400>;
164 clocks = <&rcc TIM3_K>;
166 dmas = <&dmamux1 23 0x400 0x1>,
167 <&dmamux1 24 0x400 0x1>,
168 <&dmamux1 25 0x400 0x1>,
169 <&dmamux1 26 0x400 0x1>,
170 <&dmamux1 27 0x400 0x1>,
171 <&dmamux1 28 0x400 0x1>;
172 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
176 compatible = "st,stm32-pwm";
182 compatible = "st,stm32h7-timer-trigger";
188 compatible = "st,stm32-timer-counter";
193 timers4: timer@40002000 {
194 #address-cells = <1>;
196 compatible = "st,stm32-timers";
197 reg = <0x40002000 0x400>;
198 clocks = <&rcc TIM4_K>;
200 dmas = <&dmamux1 29 0x400 0x1>,
201 <&dmamux1 30 0x400 0x1>,
202 <&dmamux1 31 0x400 0x1>,
203 <&dmamux1 32 0x400 0x1>;
204 dma-names = "ch1", "ch2", "ch3", "ch4";
208 compatible = "st,stm32-pwm";
214 compatible = "st,stm32h7-timer-trigger";
220 compatible = "st,stm32-timer-counter";
225 timers5: timer@40003000 {
226 #address-cells = <1>;
228 compatible = "st,stm32-timers";
229 reg = <0x40003000 0x400>;
230 clocks = <&rcc TIM5_K>;
232 dmas = <&dmamux1 55 0x400 0x1>,
233 <&dmamux1 56 0x400 0x1>,
234 <&dmamux1 57 0x400 0x1>,
235 <&dmamux1 58 0x400 0x1>,
236 <&dmamux1 59 0x400 0x1>,
237 <&dmamux1 60 0x400 0x1>;
238 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
242 compatible = "st,stm32-pwm";
248 compatible = "st,stm32h7-timer-trigger";
254 compatible = "st,stm32-timer-counter";
259 timers6: timer@40004000 {
260 #address-cells = <1>;
262 compatible = "st,stm32-timers";
263 reg = <0x40004000 0x400>;
264 clocks = <&rcc TIM6_K>;
266 dmas = <&dmamux1 69 0x400 0x1>;
271 compatible = "st,stm32h7-timer-trigger";
277 timers7: timer@40005000 {
278 #address-cells = <1>;
280 compatible = "st,stm32-timers";
281 reg = <0x40005000 0x400>;
282 clocks = <&rcc TIM7_K>;
284 dmas = <&dmamux1 70 0x400 0x1>;
289 compatible = "st,stm32h7-timer-trigger";
295 timers12: timer@40006000 {
296 #address-cells = <1>;
298 compatible = "st,stm32-timers";
299 reg = <0x40006000 0x400>;
300 clocks = <&rcc TIM12_K>;
305 compatible = "st,stm32-pwm";
311 compatible = "st,stm32h7-timer-trigger";
317 timers13: timer@40007000 {
318 #address-cells = <1>;
320 compatible = "st,stm32-timers";
321 reg = <0x40007000 0x400>;
322 clocks = <&rcc TIM13_K>;
327 compatible = "st,stm32-pwm";
333 compatible = "st,stm32h7-timer-trigger";
339 timers14: timer@40008000 {
340 #address-cells = <1>;
342 compatible = "st,stm32-timers";
343 reg = <0x40008000 0x400>;
344 clocks = <&rcc TIM14_K>;
349 compatible = "st,stm32-pwm";
355 compatible = "st,stm32h7-timer-trigger";
361 lptimer1: timer@40009000 {
362 #address-cells = <1>;
364 compatible = "st,stm32-lptimer";
365 reg = <0x40009000 0x400>;
366 clocks = <&rcc LPTIM1_K>;
371 compatible = "st,stm32-pwm-lp";
377 compatible = "st,stm32-lptimer-trigger";
383 compatible = "st,stm32-lptimer-counter";
389 #address-cells = <1>;
391 compatible = "st,stm32h7-spi";
392 reg = <0x4000b000 0x400>;
393 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&rcc SPI2_K>;
395 resets = <&rcc SPI2_R>;
396 dmas = <&dmamux1 39 0x400 0x05>,
397 <&dmamux1 40 0x400 0x05>;
398 dma-names = "rx", "tx";
402 i2s2: audio-controller@4000b000 {
403 compatible = "st,stm32h7-i2s";
404 #sound-dai-cells = <0>;
405 reg = <0x4000b000 0x400>;
406 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
407 dmas = <&dmamux1 39 0x400 0x01>,
408 <&dmamux1 40 0x400 0x01>;
409 dma-names = "rx", "tx";
414 #address-cells = <1>;
416 compatible = "st,stm32h7-spi";
417 reg = <0x4000c000 0x400>;
418 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&rcc SPI3_K>;
420 resets = <&rcc SPI3_R>;
421 dmas = <&dmamux1 61 0x400 0x05>,
422 <&dmamux1 62 0x400 0x05>;
423 dma-names = "rx", "tx";
427 i2s3: audio-controller@4000c000 {
428 compatible = "st,stm32h7-i2s";
429 #sound-dai-cells = <0>;
430 reg = <0x4000c000 0x400>;
431 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
432 dmas = <&dmamux1 61 0x400 0x01>,
433 <&dmamux1 62 0x400 0x01>;
434 dma-names = "rx", "tx";
438 spdifrx: audio-controller@4000d000 {
439 compatible = "st,stm32h7-spdifrx";
440 #sound-dai-cells = <0>;
441 reg = <0x4000d000 0x400>;
442 clocks = <&rcc SPDIF_K>;
443 clock-names = "kclk";
444 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
445 dmas = <&dmamux1 93 0x400 0x01>,
446 <&dmamux1 94 0x400 0x01>;
447 dma-names = "rx", "rx-ctrl";
451 usart2: serial@4000e000 {
452 compatible = "st,stm32h7-uart";
453 reg = <0x4000e000 0x400>;
454 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&rcc USART2_K>;
459 usart3: serial@4000f000 {
460 compatible = "st,stm32h7-uart";
461 reg = <0x4000f000 0x400>;
462 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&rcc USART3_K>;
467 uart4: serial@40010000 {
468 compatible = "st,stm32h7-uart";
469 reg = <0x40010000 0x400>;
470 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&rcc UART4_K>;
475 uart5: serial@40011000 {
476 compatible = "st,stm32h7-uart";
477 reg = <0x40011000 0x400>;
478 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&rcc UART5_K>;
484 compatible = "st,stm32f7-i2c";
485 reg = <0x40012000 0x400>;
486 interrupt-names = "event", "error";
487 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&rcc I2C1_K>;
490 resets = <&rcc I2C1_R>;
491 #address-cells = <1>;
497 compatible = "st,stm32f7-i2c";
498 reg = <0x40013000 0x400>;
499 interrupt-names = "event", "error";
500 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&rcc I2C2_K>;
503 resets = <&rcc I2C2_R>;
504 #address-cells = <1>;
510 compatible = "st,stm32f7-i2c";
511 reg = <0x40014000 0x400>;
512 interrupt-names = "event", "error";
513 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&rcc I2C3_K>;
516 resets = <&rcc I2C3_R>;
517 #address-cells = <1>;
523 compatible = "st,stm32f7-i2c";
524 reg = <0x40015000 0x400>;
525 interrupt-names = "event", "error";
526 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&rcc I2C5_K>;
529 resets = <&rcc I2C5_R>;
530 #address-cells = <1>;
536 compatible = "st,stm32-cec";
537 reg = <0x40016000 0x400>;
538 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&rcc CEC_K>, <&clk_lse>;
540 clock-names = "cec", "hdmi-cec";
545 compatible = "st,stm32h7-dac-core";
546 reg = <0x40017000 0x400>;
547 clocks = <&rcc DAC12>;
548 clock-names = "pclk";
549 #address-cells = <1>;
554 compatible = "st,stm32-dac";
555 #io-channels-cells = <1>;
561 compatible = "st,stm32-dac";
562 #io-channels-cells = <1>;
568 uart7: serial@40018000 {
569 compatible = "st,stm32h7-uart";
570 reg = <0x40018000 0x400>;
571 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&rcc UART7_K>;
576 uart8: serial@40019000 {
577 compatible = "st,stm32h7-uart";
578 reg = <0x40019000 0x400>;
579 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&rcc UART8_K>;
584 timers1: timer@44000000 {
585 #address-cells = <1>;
587 compatible = "st,stm32-timers";
588 reg = <0x44000000 0x400>;
589 clocks = <&rcc TIM1_K>;
591 dmas = <&dmamux1 11 0x400 0x1>,
592 <&dmamux1 12 0x400 0x1>,
593 <&dmamux1 13 0x400 0x1>,
594 <&dmamux1 14 0x400 0x1>,
595 <&dmamux1 15 0x400 0x1>,
596 <&dmamux1 16 0x400 0x1>,
597 <&dmamux1 17 0x400 0x1>;
598 dma-names = "ch1", "ch2", "ch3", "ch4",
603 compatible = "st,stm32-pwm";
609 compatible = "st,stm32h7-timer-trigger";
615 compatible = "st,stm32-timer-counter";
620 timers8: timer@44001000 {
621 #address-cells = <1>;
623 compatible = "st,stm32-timers";
624 reg = <0x44001000 0x400>;
625 clocks = <&rcc TIM8_K>;
627 dmas = <&dmamux1 47 0x400 0x1>,
628 <&dmamux1 48 0x400 0x1>,
629 <&dmamux1 49 0x400 0x1>,
630 <&dmamux1 50 0x400 0x1>,
631 <&dmamux1 51 0x400 0x1>,
632 <&dmamux1 52 0x400 0x1>,
633 <&dmamux1 53 0x400 0x1>;
634 dma-names = "ch1", "ch2", "ch3", "ch4",
639 compatible = "st,stm32-pwm";
645 compatible = "st,stm32h7-timer-trigger";
651 compatible = "st,stm32-timer-counter";
656 usart6: serial@44003000 {
657 compatible = "st,stm32h7-uart";
658 reg = <0x44003000 0x400>;
659 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&rcc USART6_K>;
665 #address-cells = <1>;
667 compatible = "st,stm32h7-spi";
668 reg = <0x44004000 0x400>;
669 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&rcc SPI1_K>;
671 resets = <&rcc SPI1_R>;
672 dmas = <&dmamux1 37 0x400 0x05>,
673 <&dmamux1 38 0x400 0x05>;
674 dma-names = "rx", "tx";
678 i2s1: audio-controller@44004000 {
679 compatible = "st,stm32h7-i2s";
680 #sound-dai-cells = <0>;
681 reg = <0x44004000 0x400>;
682 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
683 dmas = <&dmamux1 37 0x400 0x01>,
684 <&dmamux1 38 0x400 0x01>;
685 dma-names = "rx", "tx";
690 #address-cells = <1>;
692 compatible = "st,stm32h7-spi";
693 reg = <0x44005000 0x400>;
694 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&rcc SPI4_K>;
696 resets = <&rcc SPI4_R>;
697 dmas = <&dmamux1 83 0x400 0x05>,
698 <&dmamux1 84 0x400 0x05>;
699 dma-names = "rx", "tx";
703 timers15: timer@44006000 {
704 #address-cells = <1>;
706 compatible = "st,stm32-timers";
707 reg = <0x44006000 0x400>;
708 clocks = <&rcc TIM15_K>;
710 dmas = <&dmamux1 105 0x400 0x1>,
711 <&dmamux1 106 0x400 0x1>,
712 <&dmamux1 107 0x400 0x1>,
713 <&dmamux1 108 0x400 0x1>;
714 dma-names = "ch1", "up", "trig", "com";
718 compatible = "st,stm32-pwm";
724 compatible = "st,stm32h7-timer-trigger";
730 timers16: timer@44007000 {
731 #address-cells = <1>;
733 compatible = "st,stm32-timers";
734 reg = <0x44007000 0x400>;
735 clocks = <&rcc TIM16_K>;
737 dmas = <&dmamux1 109 0x400 0x1>,
738 <&dmamux1 110 0x400 0x1>;
739 dma-names = "ch1", "up";
743 compatible = "st,stm32-pwm";
748 compatible = "st,stm32h7-timer-trigger";
754 timers17: timer@44008000 {
755 #address-cells = <1>;
757 compatible = "st,stm32-timers";
758 reg = <0x44008000 0x400>;
759 clocks = <&rcc TIM17_K>;
761 dmas = <&dmamux1 111 0x400 0x1>,
762 <&dmamux1 112 0x400 0x1>;
763 dma-names = "ch1", "up";
767 compatible = "st,stm32-pwm";
773 compatible = "st,stm32h7-timer-trigger";
780 #address-cells = <1>;
782 compatible = "st,stm32h7-spi";
783 reg = <0x44009000 0x400>;
784 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&rcc SPI5_K>;
786 resets = <&rcc SPI5_R>;
787 dmas = <&dmamux1 85 0x400 0x05>,
788 <&dmamux1 86 0x400 0x05>;
789 dma-names = "rx", "tx";
794 compatible = "st,stm32h7-sai";
795 #address-cells = <1>;
797 ranges = <0 0x4400a000 0x400>;
798 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
799 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
800 resets = <&rcc SAI1_R>;
803 sai1a: audio-controller@4400a004 {
804 #sound-dai-cells = <0>;
806 compatible = "st,stm32-sai-sub-a";
808 clocks = <&rcc SAI1_K>;
809 clock-names = "sai_ck";
810 dmas = <&dmamux1 87 0x400 0x01>;
814 sai1b: audio-controller@4400a024 {
815 #sound-dai-cells = <0>;
816 compatible = "st,stm32-sai-sub-b";
818 clocks = <&rcc SAI1_K>;
819 clock-names = "sai_ck";
820 dmas = <&dmamux1 88 0x400 0x01>;
826 compatible = "st,stm32h7-sai";
827 #address-cells = <1>;
829 ranges = <0 0x4400b000 0x400>;
830 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
831 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
832 resets = <&rcc SAI2_R>;
835 sai2a: audio-controller@4400b004 {
836 #sound-dai-cells = <0>;
837 compatible = "st,stm32-sai-sub-a";
839 clocks = <&rcc SAI2_K>;
840 clock-names = "sai_ck";
841 dmas = <&dmamux1 89 0x400 0x01>;
845 sai2b: audio-controller@4400b024 {
846 #sound-dai-cells = <0>;
847 compatible = "st,stm32-sai-sub-b";
849 clocks = <&rcc SAI2_K>;
850 clock-names = "sai_ck";
851 dmas = <&dmamux1 90 0x400 0x01>;
857 compatible = "st,stm32h7-sai";
858 #address-cells = <1>;
860 ranges = <0 0x4400c000 0x400>;
861 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
862 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
863 resets = <&rcc SAI3_R>;
866 sai3a: audio-controller@4400c004 {
867 #sound-dai-cells = <0>;
868 compatible = "st,stm32-sai-sub-a";
870 clocks = <&rcc SAI3_K>;
871 clock-names = "sai_ck";
872 dmas = <&dmamux1 113 0x400 0x01>;
876 sai3b: audio-controller@4400c024 {
877 #sound-dai-cells = <0>;
878 compatible = "st,stm32-sai-sub-b";
880 clocks = <&rcc SAI3_K>;
881 clock-names = "sai_ck";
882 dmas = <&dmamux1 114 0x400 0x01>;
887 dfsdm: dfsdm@4400d000 {
888 compatible = "st,stm32mp1-dfsdm";
889 reg = <0x4400d000 0x800>;
890 clocks = <&rcc DFSDM_K>;
891 clock-names = "dfsdm";
892 #address-cells = <1>;
897 compatible = "st,stm32-dfsdm-adc";
898 #io-channel-cells = <1>;
900 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
901 dmas = <&dmamux1 101 0x400 0x01>;
907 compatible = "st,stm32-dfsdm-adc";
908 #io-channel-cells = <1>;
910 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
911 dmas = <&dmamux1 102 0x400 0x01>;
917 compatible = "st,stm32-dfsdm-adc";
918 #io-channel-cells = <1>;
920 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
921 dmas = <&dmamux1 103 0x400 0x01>;
927 compatible = "st,stm32-dfsdm-adc";
928 #io-channel-cells = <1>;
930 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
931 dmas = <&dmamux1 104 0x400 0x01>;
937 compatible = "st,stm32-dfsdm-adc";
938 #io-channel-cells = <1>;
940 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
941 dmas = <&dmamux1 91 0x400 0x01>;
947 compatible = "st,stm32-dfsdm-adc";
948 #io-channel-cells = <1>;
950 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
951 dmas = <&dmamux1 92 0x400 0x01>;
957 dma1: dma-controller@48000000 {
958 compatible = "st,stm32-dma";
959 reg = <0x48000000 0x400>;
960 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&rcc DMA1>;
974 dma2: dma-controller@48001000 {
975 compatible = "st,stm32-dma";
976 reg = <0x48001000 0x400>;
977 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&rcc DMA2>;
991 dmamux1: dma-router@48002000 {
992 compatible = "st,stm32h7-dmamux";
993 reg = <0x48002000 0x1c>;
995 dma-requests = <128>;
996 dma-masters = <&dma1 &dma2>;
998 clocks = <&rcc DMAMUX>;
1002 compatible = "st,stm32mp1-adc-core";
1003 reg = <0x48003000 0x400>;
1004 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1007 clock-names = "bus", "adc";
1008 interrupt-controller;
1009 st,syscfg = <&syscfg>;
1010 #interrupt-cells = <1>;
1011 #address-cells = <1>;
1013 status = "disabled";
1016 compatible = "st,stm32mp1-adc";
1017 #io-channel-cells = <1>;
1019 interrupt-parent = <&adc>;
1021 dmas = <&dmamux1 9 0x400 0x01>;
1023 status = "disabled";
1027 compatible = "st,stm32mp1-adc";
1028 #io-channel-cells = <1>;
1030 interrupt-parent = <&adc>;
1032 dmas = <&dmamux1 10 0x400 0x01>;
1034 status = "disabled";
1038 sdmmc3: sdmmc@48004000 {
1039 compatible = "arm,pl18x", "arm,primecell";
1040 arm,primecell-periphid = <0x10153180>;
1041 reg = <0x48004000 0x400>;
1042 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1043 interrupt-names = "cmd_irq";
1044 clocks = <&rcc SDMMC3_K>;
1045 clock-names = "apb_pclk";
1046 resets = <&rcc SDMMC3_R>;
1049 max-frequency = <120000000>;
1050 status = "disabled";
1053 usbotg_hs: usb-otg@49000000 {
1054 compatible = "snps,dwc2";
1055 reg = <0x49000000 0x10000>;
1056 clocks = <&rcc USBO_K>;
1057 clock-names = "otg";
1058 resets = <&rcc USBO_R>;
1059 reset-names = "dwc2";
1060 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1061 g-rx-fifo-size = <256>;
1062 g-np-tx-fifo-size = <32>;
1063 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1065 usb33d-supply = <&usb33>;
1066 status = "disabled";
1069 hwspinlock: hwspinlock@4c000000 {
1070 compatible = "st,stm32-hwspinlock";
1071 #hwlock-cells = <1>;
1072 reg = <0x4c000000 0x400>;
1073 clocks = <&rcc HSEM>;
1074 clock-names = "hwspinlock";
1077 ipcc: mailbox@4c001000 {
1078 compatible = "st,stm32mp1-ipcc";
1080 reg = <0x4c001000 0x400>;
1082 interrupts-extended =
1083 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1084 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1086 interrupt-names = "rx", "tx", "wakeup";
1087 clocks = <&rcc IPCC>;
1089 status = "disabled";
1092 dcmi: dcmi@4c006000 {
1093 compatible = "st,stm32-dcmi";
1094 reg = <0x4c006000 0x400>;
1095 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1096 resets = <&rcc CAMITF_R>;
1097 clocks = <&rcc DCMI>;
1098 clock-names = "mclk";
1099 dmas = <&dmamux1 75 0x400 0x0d>;
1101 status = "disabled";
1105 compatible = "st,stm32mp1-rcc", "syscon";
1106 reg = <0x50000000 0x1000>;
1111 pwr_regulators: pwr@50001000 {
1112 compatible = "st,stm32mp1,pwr-reg";
1113 reg = <0x50001000 0x10>;
1116 regulator-name = "reg11";
1117 regulator-min-microvolt = <1100000>;
1118 regulator-max-microvolt = <1100000>;
1122 regulator-name = "reg18";
1123 regulator-min-microvolt = <1800000>;
1124 regulator-max-microvolt = <1800000>;
1128 regulator-name = "usb33";
1129 regulator-min-microvolt = <3300000>;
1130 regulator-max-microvolt = <3300000>;
1134 exti: interrupt-controller@5000d000 {
1135 compatible = "st,stm32mp1-exti", "syscon";
1136 interrupt-controller;
1137 #interrupt-cells = <2>;
1138 reg = <0x5000d000 0x400>;
1141 syscfg: syscon@50020000 {
1142 compatible = "st,stm32mp157-syscfg", "syscon";
1143 reg = <0x50020000 0x400>;
1144 clocks = <&rcc SYSCFG>;
1147 lptimer2: timer@50021000 {
1148 #address-cells = <1>;
1150 compatible = "st,stm32-lptimer";
1151 reg = <0x50021000 0x400>;
1152 clocks = <&rcc LPTIM2_K>;
1153 clock-names = "mux";
1154 status = "disabled";
1157 compatible = "st,stm32-pwm-lp";
1159 status = "disabled";
1163 compatible = "st,stm32-lptimer-trigger";
1165 status = "disabled";
1169 compatible = "st,stm32-lptimer-counter";
1170 status = "disabled";
1174 lptimer3: timer@50022000 {
1175 #address-cells = <1>;
1177 compatible = "st,stm32-lptimer";
1178 reg = <0x50022000 0x400>;
1179 clocks = <&rcc LPTIM3_K>;
1180 clock-names = "mux";
1181 status = "disabled";
1184 compatible = "st,stm32-pwm-lp";
1186 status = "disabled";
1190 compatible = "st,stm32-lptimer-trigger";
1192 status = "disabled";
1196 lptimer4: timer@50023000 {
1197 compatible = "st,stm32-lptimer";
1198 reg = <0x50023000 0x400>;
1199 clocks = <&rcc LPTIM4_K>;
1200 clock-names = "mux";
1201 status = "disabled";
1204 compatible = "st,stm32-pwm-lp";
1206 status = "disabled";
1210 lptimer5: timer@50024000 {
1211 compatible = "st,stm32-lptimer";
1212 reg = <0x50024000 0x400>;
1213 clocks = <&rcc LPTIM5_K>;
1214 clock-names = "mux";
1215 status = "disabled";
1218 compatible = "st,stm32-pwm-lp";
1220 status = "disabled";
1224 vrefbuf: vrefbuf@50025000 {
1225 compatible = "st,stm32-vrefbuf";
1226 reg = <0x50025000 0x8>;
1227 regulator-min-microvolt = <1500000>;
1228 regulator-max-microvolt = <2500000>;
1229 clocks = <&rcc VREF>;
1230 status = "disabled";
1233 sai4: sai@50027000 {
1234 compatible = "st,stm32h7-sai";
1235 #address-cells = <1>;
1237 ranges = <0 0x50027000 0x400>;
1238 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1239 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1240 resets = <&rcc SAI4_R>;
1241 status = "disabled";
1243 sai4a: audio-controller@50027004 {
1244 #sound-dai-cells = <0>;
1245 compatible = "st,stm32-sai-sub-a";
1247 clocks = <&rcc SAI4_K>;
1248 clock-names = "sai_ck";
1249 dmas = <&dmamux1 99 0x400 0x01>;
1250 status = "disabled";
1253 sai4b: audio-controller@50027024 {
1254 #sound-dai-cells = <0>;
1255 compatible = "st,stm32-sai-sub-b";
1257 clocks = <&rcc SAI4_K>;
1258 clock-names = "sai_ck";
1259 dmas = <&dmamux1 100 0x400 0x01>;
1260 status = "disabled";
1264 dts: thermal@50028000 {
1265 compatible = "st,stm32-thermal";
1266 reg = <0x50028000 0x100>;
1267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&rcc TMPSENS>;
1269 clock-names = "pclk";
1270 #thermal-sensor-cells = <0>;
1271 status = "disabled";
1274 hash1: hash@54002000 {
1275 compatible = "st,stm32f756-hash";
1276 reg = <0x54002000 0x400>;
1277 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&rcc HASH1>;
1279 resets = <&rcc HASH1_R>;
1280 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1283 status = "disabled";
1286 rng1: rng@54003000 {
1287 compatible = "st,stm32-rng";
1288 reg = <0x54003000 0x400>;
1289 clocks = <&rcc RNG1_K>;
1290 resets = <&rcc RNG1_R>;
1291 status = "disabled";
1294 mdma1: dma-controller@58000000 {
1295 compatible = "st,stm32h7-mdma";
1296 reg = <0x58000000 0x1000>;
1297 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&rcc MDMA>;
1300 dma-channels = <32>;
1301 dma-requests = <48>;
1304 fmc: nand-controller@58002000 {
1305 compatible = "st,stm32mp15-fmc2";
1306 reg = <0x58002000 0x1000>,
1307 <0x80000000 0x1000>,
1308 <0x88010000 0x1000>,
1309 <0x88020000 0x1000>,
1310 <0x81000000 0x1000>,
1311 <0x89010000 0x1000>,
1312 <0x89020000 0x1000>;
1313 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1314 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1315 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1316 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1317 dma-names = "tx", "rx", "ecc";
1318 clocks = <&rcc FMC_K>;
1319 resets = <&rcc FMC_R>;
1320 status = "disabled";
1323 qspi: spi@58003000 {
1324 compatible = "st,stm32f469-qspi";
1325 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1326 reg-names = "qspi", "qspi_mm";
1327 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1328 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1329 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1330 dma-names = "tx", "rx";
1331 clocks = <&rcc QSPI_K>;
1332 resets = <&rcc QSPI_R>;
1333 status = "disabled";
1336 sdmmc1: sdmmc@58005000 {
1337 compatible = "arm,pl18x", "arm,primecell";
1338 arm,primecell-periphid = <0x10153180>;
1339 reg = <0x58005000 0x1000>;
1340 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1341 interrupt-names = "cmd_irq";
1342 clocks = <&rcc SDMMC1_K>;
1343 clock-names = "apb_pclk";
1344 resets = <&rcc SDMMC1_R>;
1347 max-frequency = <120000000>;
1348 status = "disabled";
1351 sdmmc2: sdmmc@58007000 {
1352 compatible = "arm,pl18x", "arm,primecell";
1353 arm,primecell-periphid = <0x10153180>;
1354 reg = <0x58007000 0x1000>;
1355 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1356 interrupt-names = "cmd_irq";
1357 clocks = <&rcc SDMMC2_K>;
1358 clock-names = "apb_pclk";
1359 resets = <&rcc SDMMC2_R>;
1362 max-frequency = <120000000>;
1363 status = "disabled";
1366 crc1: crc@58009000 {
1367 compatible = "st,stm32f7-crc";
1368 reg = <0x58009000 0x400>;
1369 clocks = <&rcc CRC1>;
1370 status = "disabled";
1373 stmmac_axi_config_0: stmmac-axi-config {
1374 snps,wr_osr_lmt = <0x7>;
1375 snps,rd_osr_lmt = <0x7>;
1376 snps,blen = <0 0 0 0 16 8 4>;
1379 ethernet0: ethernet@5800a000 {
1380 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1381 reg = <0x5800a000 0x2000>;
1382 reg-names = "stmmaceth";
1383 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1384 interrupt-names = "macirq";
1385 clock-names = "stmmaceth",
1391 clocks = <&rcc ETHMAC>,
1397 st,syscon = <&syscfg 0x4>;
1400 snps,en-tx-lpi-clockgating;
1401 snps,axi-config = <&stmmac_axi_config_0>;
1403 status = "disabled";
1406 usbh_ohci: usbh-ohci@5800c000 {
1407 compatible = "generic-ohci";
1408 reg = <0x5800c000 0x1000>;
1409 clocks = <&rcc USBH>;
1410 resets = <&rcc USBH_R>;
1411 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1412 status = "disabled";
1415 usbh_ehci: usbh-ehci@5800d000 {
1416 compatible = "generic-ehci";
1417 reg = <0x5800d000 0x1000>;
1418 clocks = <&rcc USBH>;
1419 resets = <&rcc USBH_R>;
1420 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1421 companion = <&usbh_ohci>;
1422 status = "disabled";
1425 ltdc: display-controller@5a001000 {
1426 compatible = "st,stm32-ltdc";
1427 reg = <0x5a001000 0x400>;
1428 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1430 clocks = <&rcc LTDC_PX>;
1431 clock-names = "lcd";
1432 resets = <&rcc LTDC_R>;
1433 status = "disabled";
1436 iwdg2: watchdog@5a002000 {
1437 compatible = "st,stm32mp1-iwdg";
1438 reg = <0x5a002000 0x400>;
1439 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1440 clock-names = "pclk", "lsi";
1441 status = "disabled";
1444 usbphyc: usbphyc@5a006000 {
1445 #address-cells = <1>;
1447 compatible = "st,stm32mp1-usbphyc";
1448 reg = <0x5a006000 0x1000>;
1449 clocks = <&rcc USBPHY_K>;
1450 resets = <&rcc USBPHY_R>;
1451 vdda1v1-supply = <®11>;
1452 vdda1v8-supply = <®18>;
1453 status = "disabled";
1455 usbphyc_port0: usb-phy@0 {
1460 usbphyc_port1: usb-phy@1 {
1466 usart1: serial@5c000000 {
1467 compatible = "st,stm32h7-uart";
1468 reg = <0x5c000000 0x400>;
1469 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&rcc USART1_K>;
1471 status = "disabled";
1474 spi6: spi@5c001000 {
1475 #address-cells = <1>;
1477 compatible = "st,stm32h7-spi";
1478 reg = <0x5c001000 0x400>;
1479 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1480 clocks = <&rcc SPI6_K>;
1481 resets = <&rcc SPI6_R>;
1482 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1483 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1484 dma-names = "rx", "tx";
1485 status = "disabled";
1488 i2c4: i2c@5c002000 {
1489 compatible = "st,stm32f7-i2c";
1490 reg = <0x5c002000 0x400>;
1491 interrupt-names = "event", "error";
1492 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1494 clocks = <&rcc I2C4_K>;
1495 resets = <&rcc I2C4_R>;
1496 #address-cells = <1>;
1498 status = "disabled";
1502 compatible = "st,stm32mp1-rtc";
1503 reg = <0x5c004000 0x400>;
1504 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1505 clock-names = "pclk", "rtc_ck";
1506 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1507 status = "disabled";
1510 bsec: efuse@5c005000 {
1511 compatible = "st,stm32mp15-bsec";
1512 reg = <0x5c005000 0x400>;
1513 #address-cells = <1>;
1523 i2c6: i2c@5c009000 {
1524 compatible = "st,stm32f7-i2c";
1525 reg = <0x5c009000 0x400>;
1526 interrupt-names = "event", "error";
1527 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1529 clocks = <&rcc I2C6_K>;
1530 resets = <&rcc I2C6_R>;
1531 #address-cells = <1>;
1533 status = "disabled";
1537 * Break node order to solve dependency probe issue between
1540 pinctrl: pin-controller@50002000 {
1541 #address-cells = <1>;
1543 compatible = "st,stm32mp157-pinctrl";
1544 ranges = <0 0x50002000 0xa400>;
1545 interrupt-parent = <&exti>;
1546 st,syscfg = <&exti 0x60 0xff>;
1547 hwlocks = <&hwspinlock 0>;
1550 gpioa: gpio@50002000 {
1553 interrupt-controller;
1554 #interrupt-cells = <2>;
1556 clocks = <&rcc GPIOA>;
1557 st,bank-name = "GPIOA";
1558 status = "disabled";
1561 gpiob: gpio@50003000 {
1564 interrupt-controller;
1565 #interrupt-cells = <2>;
1566 reg = <0x1000 0x400>;
1567 clocks = <&rcc GPIOB>;
1568 st,bank-name = "GPIOB";
1569 status = "disabled";
1572 gpioc: gpio@50004000 {
1575 interrupt-controller;
1576 #interrupt-cells = <2>;
1577 reg = <0x2000 0x400>;
1578 clocks = <&rcc GPIOC>;
1579 st,bank-name = "GPIOC";
1580 status = "disabled";
1583 gpiod: gpio@50005000 {
1586 interrupt-controller;
1587 #interrupt-cells = <2>;
1588 reg = <0x3000 0x400>;
1589 clocks = <&rcc GPIOD>;
1590 st,bank-name = "GPIOD";
1591 status = "disabled";
1594 gpioe: gpio@50006000 {
1597 interrupt-controller;
1598 #interrupt-cells = <2>;
1599 reg = <0x4000 0x400>;
1600 clocks = <&rcc GPIOE>;
1601 st,bank-name = "GPIOE";
1602 status = "disabled";
1605 gpiof: gpio@50007000 {
1608 interrupt-controller;
1609 #interrupt-cells = <2>;
1610 reg = <0x5000 0x400>;
1611 clocks = <&rcc GPIOF>;
1612 st,bank-name = "GPIOF";
1613 status = "disabled";
1616 gpiog: gpio@50008000 {
1619 interrupt-controller;
1620 #interrupt-cells = <2>;
1621 reg = <0x6000 0x400>;
1622 clocks = <&rcc GPIOG>;
1623 st,bank-name = "GPIOG";
1624 status = "disabled";
1627 gpioh: gpio@50009000 {
1630 interrupt-controller;
1631 #interrupt-cells = <2>;
1632 reg = <0x7000 0x400>;
1633 clocks = <&rcc GPIOH>;
1634 st,bank-name = "GPIOH";
1635 status = "disabled";
1638 gpioi: gpio@5000a000 {
1641 interrupt-controller;
1642 #interrupt-cells = <2>;
1643 reg = <0x8000 0x400>;
1644 clocks = <&rcc GPIOI>;
1645 st,bank-name = "GPIOI";
1646 status = "disabled";
1649 gpioj: gpio@5000b000 {
1652 interrupt-controller;
1653 #interrupt-cells = <2>;
1654 reg = <0x9000 0x400>;
1655 clocks = <&rcc GPIOJ>;
1656 st,bank-name = "GPIOJ";
1657 status = "disabled";
1660 gpiok: gpio@5000c000 {
1663 interrupt-controller;
1664 #interrupt-cells = <2>;
1665 reg = <0xa000 0x400>;
1666 clocks = <&rcc GPIOK>;
1667 st,bank-name = "GPIOK";
1668 status = "disabled";
1672 pinctrl_z: pin-controller-z@54004000 {
1673 #address-cells = <1>;
1675 compatible = "st,stm32mp157-z-pinctrl";
1676 ranges = <0 0x54004000 0x400>;
1678 interrupt-parent = <&exti>;
1679 st,syscfg = <&exti 0x60 0xff>;
1680 hwlocks = <&hwspinlock 0>;
1682 gpioz: gpio@54004000 {
1685 interrupt-controller;
1686 #interrupt-cells = <2>;
1688 clocks = <&rcc GPIOZ>;
1689 st,bank-name = "GPIOZ";
1690 st,bank-ioport = <11>;
1691 status = "disabled";
1697 compatible = "st,mlahb", "simple-bus";
1698 #address-cells = <1>;
1701 dma-ranges = <0x00000000 0x38000000 0x10000>,
1702 <0x10000000 0x10000000 0x60000>,
1703 <0x30000000 0x30000000 0x60000>;
1705 m4_rproc: m4@10000000 {
1706 compatible = "st,stm32mp1-m4";
1707 reg = <0x10000000 0x40000>,
1708 <0x30000000 0x40000>,
1709 <0x38000000 0x10000>;
1710 resets = <&rcc MCU_R>;
1711 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1712 st,syscfg-tz = <&rcc 0x000 0x1>;
1713 status = "disabled";