arch/arm/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23         };
  24
  25         psci {
  26                 compatible = "arm,psci-1.0";
  27                 method = "smc";
  28                 cpu_off = <0x84000002>;
  29                 cpu_on = <0x84000003>;
  30         };
  31
  32         intc: interrupt-controller@a0021000 {
  33                 compatible = "arm,cortex-a7-gic";
  34                 #interrupt-cells = <3>;
  35                 interrupt-controller;
  36                 reg = <0xa0021000 0x1000>,
  37                       <0xa0022000 0x2000>;
  38         };
  39
  40         timer {
  41                 compatible = "arm,armv7-timer";
  42                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  43                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  44                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  45                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  46                 interrupt-parent = <&intc>;
  47         };
  48
  49         clocks {
  50                 clk_hse: clk-hse {
  51                         #clock-cells = <0>;
  52                         compatible = "fixed-clock";
  53                         clock-frequency = <24000000>;
  54                 };
  55
  56                 clk_hsi: clk-hsi {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <64000000>;
  60                 };
  61
  62                 clk_lse: clk-lse {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32768>;
  66                 };
  67
  68                 clk_lsi: clk-lsi {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32000>;
  72                 };
  73
  74                 clk_csi: clk-csi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <4000000>;
  78                 };
  79         };
  80
  81         thermal-zones {
  82                 cpu_thermal: cpu-thermal {
  83                         polling-delay-passive = <0>;
  84                         polling-delay = <0>;
  85                         thermal-sensors = <&dts>;
  86
  87                         trips {
  88                                 cpu_alert1: cpu-alert1 {
  89                                         temperature = <85000>;
  90                                         hysteresis = <0>;
  91                                         type = "passive";
  92                                 };
  93
  94                                 cpu-crit {
  95                                         temperature = <120000>;
  96                                         hysteresis = <0>;
  97                                         type = "critical";
  98                                 };
  99                         };
 100
 101                         cooling-maps {
 102                         };
 103                 };
 104         };
 105
 106         booster: regulator-booster {
 107                 compatible = "st,stm32mp1-booster";
 108                 st,syscfg = <&syscfg>;
 109                 status = "disabled";
 110         };
 111
 112         reboot {
 113                 compatible = "syscon-reboot";
 114                 regmap = <&rcc>;
 115                 offset = <0x404>;
 116                 mask = <0x1>;
 117         };
 118
 119         soc {
 120                 compatible = "simple-bus";
 121                 #address-cells = <1>;
 122                 #size-cells = <1>;
 123                 interrupt-parent = <&intc>;
 124                 ranges;
 125
 126                 timers2: timer@40000000 {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         compatible = "st,stm32-timers";
 130                         reg = <0x40000000 0x400>;
 131                         clocks = <&rcc TIM2_K>;
 132                         clock-names = "int";
 133                         dmas = <&dmamux1 18 0x400 0x1>,
 134                                <&dmamux1 19 0x400 0x1>,
 135                                <&dmamux1 20 0x400 0x1>,
 136                                <&dmamux1 21 0x400 0x1>,
 137                                <&dmamux1 22 0x400 0x1>;
 138                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 139                         status = "disabled";
 140
 141                         pwm {
 142                                 compatible = "st,stm32-pwm";
 143                                 #pwm-cells = <3>;
 144                                 status = "disabled";
 145                         };
 146
 147                         timer@1 {
 148                                 compatible = "st,stm32h7-timer-trigger";
 149                                 reg = <1>;
 150                                 status = "disabled";
 151                         };
 152
 153                         counter {
 154                                 compatible = "st,stm32-timer-counter";
 155                                 status = "disabled";
 156                         };
 157                 };
 158
 159                 timers3: timer@40001000 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         compatible = "st,stm32-timers";
 163                         reg = <0x40001000 0x400>;
 164                         clocks = <&rcc TIM3_K>;
 165                         clock-names = "int";
 166                         dmas = <&dmamux1 23 0x400 0x1>,
 167                                <&dmamux1 24 0x400 0x1>,
 168                                <&dmamux1 25 0x400 0x1>,
 169                                <&dmamux1 26 0x400 0x1>,
 170                                <&dmamux1 27 0x400 0x1>,
 171                                <&dmamux1 28 0x400 0x1>;
 172                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 173                         status = "disabled";
 174
 175                         pwm {
 176                                 compatible = "st,stm32-pwm";
 177                                 #pwm-cells = <3>;
 178                                 status = "disabled";
 179                         };
 180
 181                         timer@2 {
 182                                 compatible = "st,stm32h7-timer-trigger";
 183                                 reg = <2>;
 184                                 status = "disabled";
 185                         };
 186
 187                         counter {
 188                                 compatible = "st,stm32-timer-counter";
 189                                 status = "disabled";
 190                         };
 191                 };
 192
 193                 timers4: timer@40002000 {
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         compatible = "st,stm32-timers";
 197                         reg = <0x40002000 0x400>;
 198                         clocks = <&rcc TIM4_K>;
 199                         clock-names = "int";
 200                         dmas = <&dmamux1 29 0x400 0x1>,
 201                                <&dmamux1 30 0x400 0x1>,
 202                                <&dmamux1 31 0x400 0x1>,
 203                                <&dmamux1 32 0x400 0x1>;
 204                         dma-names = "ch1", "ch2", "ch3", "ch4";
 205                         status = "disabled";
 206
 207                         pwm {
 208                                 compatible = "st,stm32-pwm";
 209                                 #pwm-cells = <3>;
 210                                 status = "disabled";
 211                         };
 212
 213                         timer@3 {
 214                                 compatible = "st,stm32h7-timer-trigger";
 215                                 reg = <3>;
 216                                 status = "disabled";
 217                         };
 218
 219                         counter {
 220                                 compatible = "st,stm32-timer-counter";
 221                                 status = "disabled";
 222                         };
 223                 };
 224
 225                 timers5: timer@40003000 {
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         compatible = "st,stm32-timers";
 229                         reg = <0x40003000 0x400>;
 230                         clocks = <&rcc TIM5_K>;
 231                         clock-names = "int";
 232                         dmas = <&dmamux1 55 0x400 0x1>,
 233                                <&dmamux1 56 0x400 0x1>,
 234                                <&dmamux1 57 0x400 0x1>,
 235                                <&dmamux1 58 0x400 0x1>,
 236                                <&dmamux1 59 0x400 0x1>,
 237                                <&dmamux1 60 0x400 0x1>;
 238                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 239                         status = "disabled";
 240
 241                         pwm {
 242                                 compatible = "st,stm32-pwm";
 243                                 #pwm-cells = <3>;
 244                                 status = "disabled";
 245                         };
 246
 247                         timer@4 {
 248                                 compatible = "st,stm32h7-timer-trigger";
 249                                 reg = <4>;
 250                                 status = "disabled";
 251                         };
 252
 253                         counter {
 254                                 compatible = "st,stm32-timer-counter";
 255                                 status = "disabled";
 256                         };
 257                 };
 258
 259                 timers6: timer@40004000 {
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262                         compatible = "st,stm32-timers";
 263                         reg = <0x40004000 0x400>;
 264                         clocks = <&rcc TIM6_K>;
 265                         clock-names = "int";
 266                         dmas = <&dmamux1 69 0x400 0x1>;
 267                         dma-names = "up";
 268                         status = "disabled";
 269
 270                         timer@5 {
 271                                 compatible = "st,stm32h7-timer-trigger";
 272                                 reg = <5>;
 273                                 status = "disabled";
 274                         };
 275                 };
 276
 277                 timers7: timer@40005000 {
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         compatible = "st,stm32-timers";
 281                         reg = <0x40005000 0x400>;
 282                         clocks = <&rcc TIM7_K>;
 283                         clock-names = "int";
 284                         dmas = <&dmamux1 70 0x400 0x1>;
 285                         dma-names = "up";
 286                         status = "disabled";
 287
 288                         timer@6 {
 289                                 compatible = "st,stm32h7-timer-trigger";
 290                                 reg = <6>;
 291                                 status = "disabled";
 292                         };
 293                 };
 294
 295                 timers12: timer@40006000 {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298                         compatible = "st,stm32-timers";
 299                         reg = <0x40006000 0x400>;
 300                         clocks = <&rcc TIM12_K>;
 301                         clock-names = "int";
 302                         status = "disabled";
 303
 304                         pwm {
 305                                 compatible = "st,stm32-pwm";
 306                                 #pwm-cells = <3>;
 307                                 status = "disabled";
 308                         };
 309
 310                         timer@11 {
 311                                 compatible = "st,stm32h7-timer-trigger";
 312                                 reg = <11>;
 313                                 status = "disabled";
 314                         };
 315                 };
 316
 317                 timers13: timer@40007000 {
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                         compatible = "st,stm32-timers";
 321                         reg = <0x40007000 0x400>;
 322                         clocks = <&rcc TIM13_K>;
 323                         clock-names = "int";
 324                         status = "disabled";
 325
 326                         pwm {
 327                                 compatible = "st,stm32-pwm";
 328                                 #pwm-cells = <3>;
 329                                 status = "disabled";
 330                         };
 331
 332                         timer@12 {
 333                                 compatible = "st,stm32h7-timer-trigger";
 334                                 reg = <12>;
 335                                 status = "disabled";
 336                         };
 337                 };
 338
 339                 timers14: timer@40008000 {
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         compatible = "st,stm32-timers";
 343                         reg = <0x40008000 0x400>;
 344                         clocks = <&rcc TIM14_K>;
 345                         clock-names = "int";
 346                         status = "disabled";
 347
 348                         pwm {
 349                                 compatible = "st,stm32-pwm";
 350                                 #pwm-cells = <3>;
 351                                 status = "disabled";
 352                         };
 353
 354                         timer@13 {
 355                                 compatible = "st,stm32h7-timer-trigger";
 356                                 reg = <13>;
 357                                 status = "disabled";
 358                         };
 359                 };
 360
 361                 lptimer1: timer@40009000 {
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         compatible = "st,stm32-lptimer";
 365                         reg = <0x40009000 0x400>;
 366                         clocks = <&rcc LPTIM1_K>;
 367                         clock-names = "mux";
 368                         status = "disabled";
 369
 370                         pwm {
 371                                 compatible = "st,stm32-pwm-lp";
 372                                 #pwm-cells = <3>;
 373                                 status = "disabled";
 374                         };
 375
 376                         trigger@0 {
 377                                 compatible = "st,stm32-lptimer-trigger";
 378                                 reg = <0>;
 379                                 status = "disabled";
 380                         };
 381
 382                         counter {
 383                                 compatible = "st,stm32-lptimer-counter";
 384                                 status = "disabled";
 385                         };
 386                 };
 387
 388                 spi2: spi@4000b000 {
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         compatible = "st,stm32h7-spi";
 392                         reg = <0x4000b000 0x400>;
 393                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&rcc SPI2_K>;
 395                         resets = <&rcc SPI2_R>;
 396                         dmas = <&dmamux1 39 0x400 0x05>,
 397                                <&dmamux1 40 0x400 0x05>;
 398                         dma-names = "rx", "tx";
 399                         status = "disabled";
 400                 };
 401
 402                 i2s2: audio-controller@4000b000 {
 403                         compatible = "st,stm32h7-i2s";
 404                         #sound-dai-cells = <0>;
 405                         reg = <0x4000b000 0x400>;
 406                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 407                         dmas = <&dmamux1 39 0x400 0x01>,
 408                                <&dmamux1 40 0x400 0x01>;
 409                         dma-names = "rx", "tx";
 410                         status = "disabled";
 411                 };
 412
 413                 spi3: spi@4000c000 {
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         compatible = "st,stm32h7-spi";
 417                         reg = <0x4000c000 0x400>;
 418                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 419                         clocks = <&rcc SPI3_K>;
 420                         resets = <&rcc SPI3_R>;
 421                         dmas = <&dmamux1 61 0x400 0x05>,
 422                                <&dmamux1 62 0x400 0x05>;
 423                         dma-names = "rx", "tx";
 424                         status = "disabled";
 425                 };
 426
 427                 i2s3: audio-controller@4000c000 {
 428                         compatible = "st,stm32h7-i2s";
 429                         #sound-dai-cells = <0>;
 430                         reg = <0x4000c000 0x400>;
 431                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 432                         dmas = <&dmamux1 61 0x400 0x01>,
 433                                <&dmamux1 62 0x400 0x01>;
 434                         dma-names = "rx", "tx";
 435                         status = "disabled";
 436                 };
 437
 438                 spdifrx: audio-controller@4000d000 {
 439                         compatible = "st,stm32h7-spdifrx";
 440                         #sound-dai-cells = <0>;
 441                         reg = <0x4000d000 0x400>;
 442                         clocks = <&rcc SPDIF_K>;
 443                         clock-names = "kclk";
 444                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 445                         dmas = <&dmamux1 93 0x400 0x01>,
 446                                <&dmamux1 94 0x400 0x01>;
 447                         dma-names = "rx", "rx-ctrl";
 448                         status = "disabled";
 449                 };
 450
 451                 usart2: serial@4000e000 {
 452                         compatible = "st,stm32h7-uart";
 453                         reg = <0x4000e000 0x400>;
 454                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 455                         clocks = <&rcc USART2_K>;
 456                         status = "disabled";
 457                 };
 458
 459                 usart3: serial@4000f000 {
 460                         compatible = "st,stm32h7-uart";
 461                         reg = <0x4000f000 0x400>;
 462                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&rcc USART3_K>;
 464                         status = "disabled";
 465                 };
 466
 467                 uart4: serial@40010000 {
 468                         compatible = "st,stm32h7-uart";
 469                         reg = <0x40010000 0x400>;
 470                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&rcc UART4_K>;
 472                         status = "disabled";
 473                 };
 474
 475                 uart5: serial@40011000 {
 476                         compatible = "st,stm32h7-uart";
 477                         reg = <0x40011000 0x400>;
 478                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&rcc UART5_K>;
 480                         status = "disabled";
 481                 };
 482
 483                 i2c1: i2c@40012000 {
 484                         compatible = "st,stm32f7-i2c";
 485                         reg = <0x40012000 0x400>;
 486                         interrupt-names = "event", "error";
 487                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 488                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&rcc I2C1_K>;
 490                         resets = <&rcc I2C1_R>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         status = "disabled";
 494                 };
 495
 496                 i2c2: i2c@40013000 {
 497                         compatible = "st,stm32f7-i2c";
 498                         reg = <0x40013000 0x400>;
 499                         interrupt-names = "event", "error";
 500                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 501                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 502                         clocks = <&rcc I2C2_K>;
 503                         resets = <&rcc I2C2_R>;
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         status = "disabled";
 507                 };
 508
 509                 i2c3: i2c@40014000 {
 510                         compatible = "st,stm32f7-i2c";
 511                         reg = <0x40014000 0x400>;
 512                         interrupt-names = "event", "error";
 513                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 514                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 515                         clocks = <&rcc I2C3_K>;
 516                         resets = <&rcc I2C3_R>;
 517                         #address-cells = <1>;
 518                         #size-cells = <0>;
 519                         status = "disabled";
 520                 };
 521
 522                 i2c5: i2c@40015000 {
 523                         compatible = "st,stm32f7-i2c";
 524                         reg = <0x40015000 0x400>;
 525                         interrupt-names = "event", "error";
 526                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 527                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&rcc I2C5_K>;
 529                         resets = <&rcc I2C5_R>;
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         status = "disabled";
 533                 };
 534
 535                 cec: cec@40016000 {
 536                         compatible = "st,stm32-cec";
 537                         reg = <0x40016000 0x400>;
 538                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 539                         clocks = <&rcc CEC_K>, <&clk_lse>;
 540                         clock-names = "cec", "hdmi-cec";
 541                         status = "disabled";
 542                 };
 543
 544                 dac: dac@40017000 {
 545                         compatible = "st,stm32h7-dac-core";
 546                         reg = <0x40017000 0x400>;
 547                         clocks = <&rcc DAC12>;
 548                         clock-names = "pclk";
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         status = "disabled";
 552
 553                         dac1: dac@1 {
 554                                 compatible = "st,stm32-dac";
 555                                 #io-channels-cells = <1>;
 556                                 reg = <1>;
 557                                 status = "disabled";
 558                         };
 559
 560                         dac2: dac@2 {
 561                                 compatible = "st,stm32-dac";
 562                                 #io-channels-cells = <1>;
 563                                 reg = <2>;
 564                                 status = "disabled";
 565                         };
 566                 };
 567
 568                 uart7: serial@40018000 {
 569                         compatible = "st,stm32h7-uart";
 570                         reg = <0x40018000 0x400>;
 571                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 572                         clocks = <&rcc UART7_K>;
 573                         status = "disabled";
 574                 };
 575
 576                 uart8: serial@40019000 {
 577                         compatible = "st,stm32h7-uart";
 578                         reg = <0x40019000 0x400>;
 579                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&rcc UART8_K>;
 581                         status = "disabled";
 582                 };
 583
 584                 timers1: timer@44000000 {
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         compatible = "st,stm32-timers";
 588                         reg = <0x44000000 0x400>;
 589                         clocks = <&rcc TIM1_K>;
 590                         clock-names = "int";
 591                         dmas = <&dmamux1 11 0x400 0x1>,
 592                                <&dmamux1 12 0x400 0x1>,
 593                                <&dmamux1 13 0x400 0x1>,
 594                                <&dmamux1 14 0x400 0x1>,
 595                                <&dmamux1 15 0x400 0x1>,
 596                                <&dmamux1 16 0x400 0x1>,
 597                                <&dmamux1 17 0x400 0x1>;
 598                         dma-names = "ch1", "ch2", "ch3", "ch4",
 599                                     "up", "trig", "com";
 600                         status = "disabled";
 601
 602                         pwm {
 603                                 compatible = "st,stm32-pwm";
 604                                 #pwm-cells = <3>;
 605                                 status = "disabled";
 606                         };
 607
 608                         timer@0 {
 609                                 compatible = "st,stm32h7-timer-trigger";
 610                                 reg = <0>;
 611                                 status = "disabled";
 612                         };
 613
 614                         counter {
 615                                 compatible = "st,stm32-timer-counter";
 616                                 status = "disabled";
 617                         };
 618                 };
 619
 620                 timers8: timer@44001000 {
 621                         #address-cells = <1>;
 622                         #size-cells = <0>;
 623                         compatible = "st,stm32-timers";
 624                         reg = <0x44001000 0x400>;
 625                         clocks = <&rcc TIM8_K>;
 626                         clock-names = "int";
 627                         dmas = <&dmamux1 47 0x400 0x1>,
 628                                <&dmamux1 48 0x400 0x1>,
 629                                <&dmamux1 49 0x400 0x1>,
 630                                <&dmamux1 50 0x400 0x1>,
 631                                <&dmamux1 51 0x400 0x1>,
 632                                <&dmamux1 52 0x400 0x1>,
 633                                <&dmamux1 53 0x400 0x1>;
 634                         dma-names = "ch1", "ch2", "ch3", "ch4",
 635                                     "up", "trig", "com";
 636                         status = "disabled";
 637
 638                         pwm {
 639                                 compatible = "st,stm32-pwm";
 640                                 #pwm-cells = <3>;
 641                                 status = "disabled";
 642                         };
 643
 644                         timer@7 {
 645                                 compatible = "st,stm32h7-timer-trigger";
 646                                 reg = <7>;
 647                                 status = "disabled";
 648                         };
 649
 650                         counter {
 651                                 compatible = "st,stm32-timer-counter";
 652                                 status = "disabled";
 653                         };
 654                 };
 655
 656                 usart6: serial@44003000 {
 657                         compatible = "st,stm32h7-uart";
 658                         reg = <0x44003000 0x400>;
 659                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&rcc USART6_K>;
 661                         status = "disabled";
 662                 };
 663
 664                 spi1: spi@44004000 {
 665                         #address-cells = <1>;
 666                         #size-cells = <0>;
 667                         compatible = "st,stm32h7-spi";
 668                         reg = <0x44004000 0x400>;
 669                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&rcc SPI1_K>;
 671                         resets = <&rcc SPI1_R>;
 672                         dmas = <&dmamux1 37 0x400 0x05>,
 673                                <&dmamux1 38 0x400 0x05>;
 674                         dma-names = "rx", "tx";
 675                         status = "disabled";
 676                 };
 677
 678                 i2s1: audio-controller@44004000 {
 679                         compatible = "st,stm32h7-i2s";
 680                         #sound-dai-cells = <0>;
 681                         reg = <0x44004000 0x400>;
 682                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 683                         dmas = <&dmamux1 37 0x400 0x01>,
 684                                <&dmamux1 38 0x400 0x01>;
 685                         dma-names = "rx", "tx";
 686                         status = "disabled";
 687                 };
 688
 689                 spi4: spi@44005000 {
 690                         #address-cells = <1>;
 691                         #size-cells = <0>;
 692                         compatible = "st,stm32h7-spi";
 693                         reg = <0x44005000 0x400>;
 694                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&rcc SPI4_K>;
 696                         resets = <&rcc SPI4_R>;
 697                         dmas = <&dmamux1 83 0x400 0x05>,
 698                                <&dmamux1 84 0x400 0x05>;
 699                         dma-names = "rx", "tx";
 700                         status = "disabled";
 701                 };
 702
 703                 timers15: timer@44006000 {
 704                         #address-cells = <1>;
 705                         #size-cells = <0>;
 706                         compatible = "st,stm32-timers";
 707                         reg = <0x44006000 0x400>;
 708                         clocks = <&rcc TIM15_K>;
 709                         clock-names = "int";
 710                         dmas = <&dmamux1 105 0x400 0x1>,
 711                                <&dmamux1 106 0x400 0x1>,
 712                                <&dmamux1 107 0x400 0x1>,
 713                                <&dmamux1 108 0x400 0x1>;
 714                         dma-names = "ch1", "up", "trig", "com";
 715                         status = "disabled";
 716
 717                         pwm {
 718                                 compatible = "st,stm32-pwm";
 719                                 #pwm-cells = <3>;
 720                                 status = "disabled";
 721                         };
 722
 723                         timer@14 {
 724                                 compatible = "st,stm32h7-timer-trigger";
 725                                 reg = <14>;
 726                                 status = "disabled";
 727                         };
 728                 };
 729
 730                 timers16: timer@44007000 {
 731                         #address-cells = <1>;
 732                         #size-cells = <0>;
 733                         compatible = "st,stm32-timers";
 734                         reg = <0x44007000 0x400>;
 735                         clocks = <&rcc TIM16_K>;
 736                         clock-names = "int";
 737                         dmas = <&dmamux1 109 0x400 0x1>,
 738                                <&dmamux1 110 0x400 0x1>;
 739                         dma-names = "ch1", "up";
 740                         status = "disabled";
 741
 742                         pwm {
 743                                 compatible = "st,stm32-pwm";
 744                                 #pwm-cells = <3>;
 745                                 status = "disabled";
 746                         };
 747                         timer@15 {
 748                                 compatible = "st,stm32h7-timer-trigger";
 749                                 reg = <15>;
 750                                 status = "disabled";
 751                         };
 752                 };
 753
 754                 timers17: timer@44008000 {
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         compatible = "st,stm32-timers";
 758                         reg = <0x44008000 0x400>;
 759                         clocks = <&rcc TIM17_K>;
 760                         clock-names = "int";
 761                         dmas = <&dmamux1 111 0x400 0x1>,
 762                                <&dmamux1 112 0x400 0x1>;
 763                         dma-names = "ch1", "up";
 764                         status = "disabled";
 765
 766                         pwm {
 767                                 compatible = "st,stm32-pwm";
 768                                 #pwm-cells = <3>;
 769                                 status = "disabled";
 770                         };
 771
 772                         timer@16 {
 773                                 compatible = "st,stm32h7-timer-trigger";
 774                                 reg = <16>;
 775                                 status = "disabled";
 776                         };
 777                 };
 778
 779                 spi5: spi@44009000 {
 780                         #address-cells = <1>;
 781                         #size-cells = <0>;
 782                         compatible = "st,stm32h7-spi";
 783                         reg = <0x44009000 0x400>;
 784                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 785                         clocks = <&rcc SPI5_K>;
 786                         resets = <&rcc SPI5_R>;
 787                         dmas = <&dmamux1 85 0x400 0x05>,
 788                                <&dmamux1 86 0x400 0x05>;
 789                         dma-names = "rx", "tx";
 790                         status = "disabled";
 791                 };
 792
 793                 sai1: sai@4400a000 {
 794                         compatible = "st,stm32h7-sai";
 795                         #address-cells = <1>;
 796                         #size-cells = <1>;
 797                         ranges = <0 0x4400a000 0x400>;
 798                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 799                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 800                         resets = <&rcc SAI1_R>;
 801                         status = "disabled";
 802
 803                         sai1a: audio-controller@4400a004 {
 804                                 #sound-dai-cells = <0>;
 805
 806                                 compatible = "st,stm32-sai-sub-a";
 807                                 reg = <0x4 0x1c>;
 808                                 clocks = <&rcc SAI1_K>;
 809                                 clock-names = "sai_ck";
 810                                 dmas = <&dmamux1 87 0x400 0x01>;
 811                                 status = "disabled";
 812                         };
 813
 814                         sai1b: audio-controller@4400a024 {
 815                                 #sound-dai-cells = <0>;
 816                                 compatible = "st,stm32-sai-sub-b";
 817                                 reg = <0x24 0x1c>;
 818                                 clocks = <&rcc SAI1_K>;
 819                                 clock-names = "sai_ck";
 820                                 dmas = <&dmamux1 88 0x400 0x01>;
 821                                 status = "disabled";
 822                         };
 823                 };
 824
 825                 sai2: sai@4400b000 {
 826                         compatible = "st,stm32h7-sai";
 827                         #address-cells = <1>;
 828                         #size-cells = <1>;
 829                         ranges = <0 0x4400b000 0x400>;
 830                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 831                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 832                         resets = <&rcc SAI2_R>;
 833                         status = "disabled";
 834
 835                         sai2a: audio-controller@4400b004 {
 836                                 #sound-dai-cells = <0>;
 837                                 compatible = "st,stm32-sai-sub-a";
 838                                 reg = <0x4 0x1c>;
 839                                 clocks = <&rcc SAI2_K>;
 840                                 clock-names = "sai_ck";
 841                                 dmas = <&dmamux1 89 0x400 0x01>;
 842                                 status = "disabled";
 843                         };
 844
 845                         sai2b: audio-controller@4400b024 {
 846                                 #sound-dai-cells = <0>;
 847                                 compatible = "st,stm32-sai-sub-b";
 848                                 reg = <0x24 0x1c>;
 849                                 clocks = <&rcc SAI2_K>;
 850                                 clock-names = "sai_ck";
 851                                 dmas = <&dmamux1 90 0x400 0x01>;
 852                                 status = "disabled";
 853                         };
 854                 };
 855
 856                 sai3: sai@4400c000 {
 857                         compatible = "st,stm32h7-sai";
 858                         #address-cells = <1>;
 859                         #size-cells = <1>;
 860                         ranges = <0 0x4400c000 0x400>;
 861                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 862                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 863                         resets = <&rcc SAI3_R>;
 864                         status = "disabled";
 865
 866                         sai3a: audio-controller@4400c004 {
 867                                 #sound-dai-cells = <0>;
 868                                 compatible = "st,stm32-sai-sub-a";
 869                                 reg = <0x04 0x1c>;
 870                                 clocks = <&rcc SAI3_K>;
 871                                 clock-names = "sai_ck";
 872                                 dmas = <&dmamux1 113 0x400 0x01>;
 873                                 status = "disabled";
 874                         };
 875
 876                         sai3b: audio-controller@4400c024 {
 877                                 #sound-dai-cells = <0>;
 878                                 compatible = "st,stm32-sai-sub-b";
 879                                 reg = <0x24 0x1c>;
 880                                 clocks = <&rcc SAI3_K>;
 881                                 clock-names = "sai_ck";
 882                                 dmas = <&dmamux1 114 0x400 0x01>;
 883                                 status = "disabled";
 884                         };
 885                 };
 886
 887                 dfsdm: dfsdm@4400d000 {
 888                         compatible = "st,stm32mp1-dfsdm";
 889                         reg = <0x4400d000 0x800>;
 890                         clocks = <&rcc DFSDM_K>;
 891                         clock-names = "dfsdm";
 892                         #address-cells = <1>;
 893                         #size-cells = <0>;
 894                         status = "disabled";
 895
 896                         dfsdm0: filter@0 {
 897                                 compatible = "st,stm32-dfsdm-adc";
 898                                 #io-channel-cells = <1>;
 899                                 reg = <0>;
 900                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 901                                 dmas = <&dmamux1 101 0x400 0x01>;
 902                                 dma-names = "rx";
 903                                 status = "disabled";
 904                         };
 905
 906                         dfsdm1: filter@1 {
 907                                 compatible = "st,stm32-dfsdm-adc";
 908                                 #io-channel-cells = <1>;
 909                                 reg = <1>;
 910                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 911                                 dmas = <&dmamux1 102 0x400 0x01>;
 912                                 dma-names = "rx";
 913                                 status = "disabled";
 914                         };
 915
 916                         dfsdm2: filter@2 {
 917                                 compatible = "st,stm32-dfsdm-adc";
 918                                 #io-channel-cells = <1>;
 919                                 reg = <2>;
 920                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 921                                 dmas = <&dmamux1 103 0x400 0x01>;
 922                                 dma-names = "rx";
 923                                 status = "disabled";
 924                         };
 925
 926                         dfsdm3: filter@3 {
 927                                 compatible = "st,stm32-dfsdm-adc";
 928                                 #io-channel-cells = <1>;
 929                                 reg = <3>;
 930                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 931                                 dmas = <&dmamux1 104 0x400 0x01>;
 932                                 dma-names = "rx";
 933                                 status = "disabled";
 934                         };
 935
 936                         dfsdm4: filter@4 {
 937                                 compatible = "st,stm32-dfsdm-adc";
 938                                 #io-channel-cells = <1>;
 939                                 reg = <4>;
 940                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 941                                 dmas = <&dmamux1 91 0x400 0x01>;
 942                                 dma-names = "rx";
 943                                 status = "disabled";
 944                         };
 945
 946                         dfsdm5: filter@5 {
 947                                 compatible = "st,stm32-dfsdm-adc";
 948                                 #io-channel-cells = <1>;
 949                                 reg = <5>;
 950                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 951                                 dmas = <&dmamux1 92 0x400 0x01>;
 952                                 dma-names = "rx";
 953                                 status = "disabled";
 954                         };
 955                 };
 956
 957                 dma1: dma-controller@48000000 {
 958                         compatible = "st,stm32-dma";
 959                         reg = <0x48000000 0x400>;
 960                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 961                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 962                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 963                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 964                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 965                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 966                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 967                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 968                         clocks = <&rcc DMA1>;
 969                         #dma-cells = <4>;
 970                         st,mem2mem;
 971                         dma-requests = <8>;
 972                 };
 973
 974                 dma2: dma-controller@48001000 {
 975                         compatible = "st,stm32-dma";
 976                         reg = <0x48001000 0x400>;
 977                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 978                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 979                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 980                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 981                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 982                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 983                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 984                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 985                         clocks = <&rcc DMA2>;
 986                         #dma-cells = <4>;
 987                         st,mem2mem;
 988                         dma-requests = <8>;
 989                 };
 990
 991                 dmamux1: dma-router@48002000 {
 992                         compatible = "st,stm32h7-dmamux";
 993                         reg = <0x48002000 0x1c>;
 994                         #dma-cells = <3>;
 995                         dma-requests = <128>;
 996                         dma-masters = <&dma1 &dma2>;
 997                         dma-channels = <16>;
 998                         clocks = <&rcc DMAMUX>;
 999                 };
1000
1001                 adc: adc@48003000 {
1002                         compatible = "st,stm32mp1-adc-core";
1003                         reg = <0x48003000 0x400>;
1004                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1005                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1006                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1007                         clock-names = "bus", "adc";
1008                         interrupt-controller;
1009                         st,syscfg = <&syscfg>;
1010                         #interrupt-cells = <1>;
1011                         #address-cells = <1>;
1012                         #size-cells = <0>;
1013                         status = "disabled";
1014
1015                         adc1: adc@0 {
1016                                 compatible = "st,stm32mp1-adc";
1017                                 #io-channel-cells = <1>;
1018                                 reg = <0x0>;
1019                                 interrupt-parent = <&adc>;
1020                                 interrupts = <0>;
1021                                 dmas = <&dmamux1 9 0x400 0x01>;
1022                                 dma-names = "rx";
1023                                 status = "disabled";
1024                         };
1025
1026                         adc2: adc@100 {
1027                                 compatible = "st,stm32mp1-adc";
1028                                 #io-channel-cells = <1>;
1029                                 reg = <0x100>;
1030                                 interrupt-parent = <&adc>;
1031                                 interrupts = <1>;
1032                                 dmas = <&dmamux1 10 0x400 0x01>;
1033                                 dma-names = "rx";
1034                                 status = "disabled";
1035                         };
1036                 };
1037
1038                 sdmmc3: sdmmc@48004000 {
1039                         compatible = "arm,pl18x", "arm,primecell";
1040                         arm,primecell-periphid = <0x10153180>;
1041                         reg = <0x48004000 0x400>;
1042                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1043                         interrupt-names = "cmd_irq";
1044                         clocks = <&rcc SDMMC3_K>;
1045                         clock-names = "apb_pclk";
1046                         resets = <&rcc SDMMC3_R>;
1047                         cap-sd-highspeed;
1048                         cap-mmc-highspeed;
1049                         max-frequency = <120000000>;
1050                         status = "disabled";
1051                 };
1052
1053                 usbotg_hs: usb-otg@49000000 {
1054                         compatible = "snps,dwc2";
1055                         reg = <0x49000000 0x10000>;
1056                         clocks = <&rcc USBO_K>;
1057                         clock-names = "otg";
1058                         resets = <&rcc USBO_R>;
1059                         reset-names = "dwc2";
1060                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1061                         g-rx-fifo-size = <256>;
1062                         g-np-tx-fifo-size = <32>;
1063                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1064                         dr_mode = "otg";
1065                         usb33d-supply = <&usb33>;
1066                         status = "disabled";
1067                 };
1068
1069                 hwspinlock: hwspinlock@4c000000 {
1070                         compatible = "st,stm32-hwspinlock";
1071                         #hwlock-cells = <1>;
1072                         reg = <0x4c000000 0x400>;
1073                         clocks = <&rcc HSEM>;
1074                         clock-names = "hwspinlock";
1075                 };
1076
1077                 ipcc: mailbox@4c001000 {
1078                         compatible = "st,stm32mp1-ipcc";
1079                         #mbox-cells = <1>;
1080                         reg = <0x4c001000 0x400>;
1081                         st,proc-id = <0>;
1082                         interrupts-extended =
1083                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1084                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1085                                 <&exti 61 1>;
1086                         interrupt-names = "rx", "tx", "wakeup";
1087                         clocks = <&rcc IPCC>;
1088                         wakeup-source;
1089                         status = "disabled";
1090                 };
1091
1092                 dcmi: dcmi@4c006000 {
1093                         compatible = "st,stm32-dcmi";
1094                         reg = <0x4c006000 0x400>;
1095                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1096                         resets = <&rcc CAMITF_R>;
1097                         clocks = <&rcc DCMI>;
1098                         clock-names = "mclk";
1099                         dmas = <&dmamux1 75 0x400 0x0d>;
1100                         dma-names = "tx";
1101                         status = "disabled";
1102                 };
1103
1104                 rcc: rcc@50000000 {
1105                         compatible = "st,stm32mp1-rcc", "syscon";
1106                         reg = <0x50000000 0x1000>;
1107                         #clock-cells = <1>;
1108                         #reset-cells = <1>;
1109                 };
1110
1111                 pwr_regulators: pwr@50001000 {
1112                         compatible = "st,stm32mp1,pwr-reg";
1113                         reg = <0x50001000 0x10>;
1114
1115                         reg11: reg11 {
1116                                 regulator-name = "reg11";
1117                                 regulator-min-microvolt = <1100000>;
1118                                 regulator-max-microvolt = <1100000>;
1119                         };
1120
1121                         reg18: reg18 {
1122                                 regulator-name = "reg18";
1123                                 regulator-min-microvolt = <1800000>;
1124                                 regulator-max-microvolt = <1800000>;
1125                         };
1126
1127                         usb33: usb33 {
1128                                 regulator-name = "usb33";
1129                                 regulator-min-microvolt = <3300000>;
1130                                 regulator-max-microvolt = <3300000>;
1131                         };
1132                 };
1133
1134                 exti: interrupt-controller@5000d000 {
1135                         compatible = "st,stm32mp1-exti", "syscon";
1136                         interrupt-controller;
1137                         #interrupt-cells = <2>;
1138                         reg = <0x5000d000 0x400>;
1139                 };
1140
1141                 syscfg: syscon@50020000 {
1142                         compatible = "st,stm32mp157-syscfg", "syscon";
1143                         reg = <0x50020000 0x400>;
1144                         clocks = <&rcc SYSCFG>;
1145                 };
1146
1147                 lptimer2: timer@50021000 {
1148                         #address-cells = <1>;
1149                         #size-cells = <0>;
1150                         compatible = "st,stm32-lptimer";
1151                         reg = <0x50021000 0x400>;
1152                         clocks = <&rcc LPTIM2_K>;
1153                         clock-names = "mux";
1154                         status = "disabled";
1155
1156                         pwm {
1157                                 compatible = "st,stm32-pwm-lp";
1158                                 #pwm-cells = <3>;
1159                                 status = "disabled";
1160                         };
1161
1162                         trigger@1 {
1163                                 compatible = "st,stm32-lptimer-trigger";
1164                                 reg = <1>;
1165                                 status = "disabled";
1166                         };
1167
1168                         counter {
1169                                 compatible = "st,stm32-lptimer-counter";
1170                                 status = "disabled";
1171                         };
1172                 };
1173
1174                 lptimer3: timer@50022000 {
1175                         #address-cells = <1>;
1176                         #size-cells = <0>;
1177                         compatible = "st,stm32-lptimer";
1178                         reg = <0x50022000 0x400>;
1179                         clocks = <&rcc LPTIM3_K>;
1180                         clock-names = "mux";
1181                         status = "disabled";
1182
1183                         pwm {
1184                                 compatible = "st,stm32-pwm-lp";
1185                                 #pwm-cells = <3>;
1186                                 status = "disabled";
1187                         };
1188
1189                         trigger@2 {
1190                                 compatible = "st,stm32-lptimer-trigger";
1191                                 reg = <2>;
1192                                 status = "disabled";
1193                         };
1194                 };
1195
1196                 lptimer4: timer@50023000 {
1197                         compatible = "st,stm32-lptimer";
1198                         reg = <0x50023000 0x400>;
1199                         clocks = <&rcc LPTIM4_K>;
1200                         clock-names = "mux";
1201                         status = "disabled";
1202
1203                         pwm {
1204                                 compatible = "st,stm32-pwm-lp";
1205                                 #pwm-cells = <3>;
1206                                 status = "disabled";
1207                         };
1208                 };
1209
1210                 lptimer5: timer@50024000 {
1211                         compatible = "st,stm32-lptimer";
1212                         reg = <0x50024000 0x400>;
1213                         clocks = <&rcc LPTIM5_K>;
1214                         clock-names = "mux";
1215                         status = "disabled";
1216
1217                         pwm {
1218                                 compatible = "st,stm32-pwm-lp";
1219                                 #pwm-cells = <3>;
1220                                 status = "disabled";
1221                         };
1222                 };
1223
1224                 vrefbuf: vrefbuf@50025000 {
1225                         compatible = "st,stm32-vrefbuf";
1226                         reg = <0x50025000 0x8>;
1227                         regulator-min-microvolt = <1500000>;
1228                         regulator-max-microvolt = <2500000>;
1229                         clocks = <&rcc VREF>;
1230                         status = "disabled";
1231                 };
1232
1233                 sai4: sai@50027000 {
1234                         compatible = "st,stm32h7-sai";
1235                         #address-cells = <1>;
1236                         #size-cells = <1>;
1237                         ranges = <0 0x50027000 0x400>;
1238                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1239                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1240                         resets = <&rcc SAI4_R>;
1241                         status = "disabled";
1242
1243                         sai4a: audio-controller@50027004 {
1244                                 #sound-dai-cells = <0>;
1245                                 compatible = "st,stm32-sai-sub-a";
1246                                 reg = <0x04 0x1c>;
1247                                 clocks = <&rcc SAI4_K>;
1248                                 clock-names = "sai_ck";
1249                                 dmas = <&dmamux1 99 0x400 0x01>;
1250                                 status = "disabled";
1251                         };
1252
1253                         sai4b: audio-controller@50027024 {
1254                                 #sound-dai-cells = <0>;
1255                                 compatible = "st,stm32-sai-sub-b";
1256                                 reg = <0x24 0x1c>;
1257                                 clocks = <&rcc SAI4_K>;
1258                                 clock-names = "sai_ck";
1259                                 dmas = <&dmamux1 100 0x400 0x01>;
1260                                 status = "disabled";
1261                         };
1262                 };
1263
1264                 dts: thermal@50028000 {
1265                         compatible = "st,stm32-thermal";
1266                         reg = <0x50028000 0x100>;
1267                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1268                         clocks = <&rcc TMPSENS>;
1269                         clock-names = "pclk";
1270                         #thermal-sensor-cells = <0>;
1271                         status = "disabled";
1272                 };
1273
1274                 hash1: hash@54002000 {
1275                         compatible = "st,stm32f756-hash";
1276                         reg = <0x54002000 0x400>;
1277                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1278                         clocks = <&rcc HASH1>;
1279                         resets = <&rcc HASH1_R>;
1280                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1281                         dma-names = "in";
1282                         dma-maxburst = <2>;
1283                         status = "disabled";
1284                 };
1285
1286                 rng1: rng@54003000 {
1287                         compatible = "st,stm32-rng";
1288                         reg = <0x54003000 0x400>;
1289                         clocks = <&rcc RNG1_K>;
1290                         resets = <&rcc RNG1_R>;
1291                         status = "disabled";
1292                 };
1293
1294                 mdma1: dma-controller@58000000 {
1295                         compatible = "st,stm32h7-mdma";
1296                         reg = <0x58000000 0x1000>;
1297                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1298                         clocks = <&rcc MDMA>;
1299                         #dma-cells = <5>;
1300                         dma-channels = <32>;
1301                         dma-requests = <48>;
1302                 };
1303
1304                 fmc: nand-controller@58002000 {
1305                         compatible = "st,stm32mp15-fmc2";
1306                         reg = <0x58002000 0x1000>,
1307                               <0x80000000 0x1000>,
1308                               <0x88010000 0x1000>,
1309                               <0x88020000 0x1000>,
1310                               <0x81000000 0x1000>,
1311                               <0x89010000 0x1000>,
1312                               <0x89020000 0x1000>;
1313                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1314                         dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1315                                <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1316                                <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1317                         dma-names = "tx", "rx", "ecc";
1318                         clocks = <&rcc FMC_K>;
1319                         resets = <&rcc FMC_R>;
1320                         status = "disabled";
1321                 };
1322
1323                 qspi: spi@58003000 {
1324                         compatible = "st,stm32f469-qspi";
1325                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1326                         reg-names = "qspi", "qspi_mm";
1327                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1328                         dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1329                                <&mdma1 22 0x10 0x100008 0x0 0x0>;
1330                         dma-names = "tx", "rx";
1331                         clocks = <&rcc QSPI_K>;
1332                         resets = <&rcc QSPI_R>;
1333                         status = "disabled";
1334                 };
1335
1336                 sdmmc1: sdmmc@58005000 {
1337                         compatible = "arm,pl18x", "arm,primecell";
1338                         arm,primecell-periphid = <0x10153180>;
1339                         reg = <0x58005000 0x1000>;
1340                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1341                         interrupt-names = "cmd_irq";
1342                         clocks = <&rcc SDMMC1_K>;
1343                         clock-names = "apb_pclk";
1344                         resets = <&rcc SDMMC1_R>;
1345                         cap-sd-highspeed;
1346                         cap-mmc-highspeed;
1347                         max-frequency = <120000000>;
1348                         status = "disabled";
1349                 };
1350
1351                 sdmmc2: sdmmc@58007000 {
1352                         compatible = "arm,pl18x", "arm,primecell";
1353                         arm,primecell-periphid = <0x10153180>;
1354                         reg = <0x58007000 0x1000>;
1355                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1356                         interrupt-names = "cmd_irq";
1357                         clocks = <&rcc SDMMC2_K>;
1358                         clock-names = "apb_pclk";
1359                         resets = <&rcc SDMMC2_R>;
1360                         cap-sd-highspeed;
1361                         cap-mmc-highspeed;
1362                         max-frequency = <120000000>;
1363                         status = "disabled";
1364                 };
1365
1366                 crc1: crc@58009000 {
1367                         compatible = "st,stm32f7-crc";
1368                         reg = <0x58009000 0x400>;
1369                         clocks = <&rcc CRC1>;
1370                         status = "disabled";
1371                 };
1372
1373                 stmmac_axi_config_0: stmmac-axi-config {
1374                         snps,wr_osr_lmt = <0x7>;
1375                         snps,rd_osr_lmt = <0x7>;
1376                         snps,blen = <0 0 0 0 16 8 4>;
1377                 };
1378
1379                 ethernet0: ethernet@5800a000 {
1380                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1381                         reg = <0x5800a000 0x2000>;
1382                         reg-names = "stmmaceth";
1383                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1384                         interrupt-names = "macirq";
1385                         clock-names = "stmmaceth",
1386                                       "mac-clk-tx",
1387                                       "mac-clk-rx",
1388                                       "eth-ck",
1389                                       "ethstp",
1390                                       "syscfg-clk";
1391                         clocks = <&rcc ETHMAC>,
1392                                  <&rcc ETHTX>,
1393                                  <&rcc ETHRX>,
1394                                  <&rcc ETHCK_K>,
1395                                  <&rcc ETHSTP>,
1396                                  <&rcc SYSCFG>;
1397                         st,syscon = <&syscfg 0x4>;
1398                         snps,mixed-burst;
1399                         snps,pbl = <2>;
1400                         snps,en-tx-lpi-clockgating;
1401                         snps,axi-config = <&stmmac_axi_config_0>;
1402                         snps,tso;
1403                         status = "disabled";
1404                 };
1405
1406                 usbh_ohci: usbh-ohci@5800c000 {
1407                         compatible = "generic-ohci";
1408                         reg = <0x5800c000 0x1000>;
1409                         clocks = <&rcc USBH>;
1410                         resets = <&rcc USBH_R>;
1411                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1412                         status = "disabled";
1413                 };
1414
1415                 usbh_ehci: usbh-ehci@5800d000 {
1416                         compatible = "generic-ehci";
1417                         reg = <0x5800d000 0x1000>;
1418                         clocks = <&rcc USBH>;
1419                         resets = <&rcc USBH_R>;
1420                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1421                         companion = <&usbh_ohci>;
1422                         status = "disabled";
1423                 };
1424
1425                 ltdc: display-controller@5a001000 {
1426                         compatible = "st,stm32-ltdc";
1427                         reg = <0x5a001000 0x400>;
1428                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1429                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1430                         clocks = <&rcc LTDC_PX>;
1431                         clock-names = "lcd";
1432                         resets = <&rcc LTDC_R>;
1433                         status = "disabled";
1434                 };
1435
1436                 iwdg2: watchdog@5a002000 {
1437                         compatible = "st,stm32mp1-iwdg";
1438                         reg = <0x5a002000 0x400>;
1439                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1440                         clock-names = "pclk", "lsi";
1441                         status = "disabled";
1442                 };
1443
1444                 usbphyc: usbphyc@5a006000 {
1445                         #address-cells = <1>;
1446                         #size-cells = <0>;
1447                         compatible = "st,stm32mp1-usbphyc";
1448                         reg = <0x5a006000 0x1000>;
1449                         clocks = <&rcc USBPHY_K>;
1450                         resets = <&rcc USBPHY_R>;
1451                         vdda1v1-supply = <&reg11>;
1452                         vdda1v8-supply = <&reg18>;
1453                         status = "disabled";
1454
1455                         usbphyc_port0: usb-phy@0 {
1456                                 #phy-cells = <0>;
1457                                 reg = <0>;
1458                         };
1459
1460                         usbphyc_port1: usb-phy@1 {
1461                                 #phy-cells = <1>;
1462                                 reg = <1>;
1463                         };
1464                 };
1465
1466                 usart1: serial@5c000000 {
1467                         compatible = "st,stm32h7-uart";
1468                         reg = <0x5c000000 0x400>;
1469                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1470                         clocks = <&rcc USART1_K>;
1471                         status = "disabled";
1472                 };
1473
1474                 spi6: spi@5c001000 {
1475                         #address-cells = <1>;
1476                         #size-cells = <0>;
1477                         compatible = "st,stm32h7-spi";
1478                         reg = <0x5c001000 0x400>;
1479                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1480                         clocks = <&rcc SPI6_K>;
1481                         resets = <&rcc SPI6_R>;
1482                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1483                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1484                         dma-names = "rx", "tx";
1485                         status = "disabled";
1486                 };
1487
1488                 i2c4: i2c@5c002000 {
1489                         compatible = "st,stm32f7-i2c";
1490                         reg = <0x5c002000 0x400>;
1491                         interrupt-names = "event", "error";
1492                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1493                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1494                         clocks = <&rcc I2C4_K>;
1495                         resets = <&rcc I2C4_R>;
1496                         #address-cells = <1>;
1497                         #size-cells = <0>;
1498                         status = "disabled";
1499                 };
1500
1501                 rtc: rtc@5c004000 {
1502                         compatible = "st,stm32mp1-rtc";
1503                         reg = <0x5c004000 0x400>;
1504                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1505                         clock-names = "pclk", "rtc_ck";
1506                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1507                         status = "disabled";
1508                 };
1509
1510                 bsec: efuse@5c005000 {
1511                         compatible = "st,stm32mp15-bsec";
1512                         reg = <0x5c005000 0x400>;
1513                         #address-cells = <1>;
1514                         #size-cells = <1>;
1515                         ts_cal1: calib@5c {
1516                                 reg = <0x5c 0x2>;
1517                         };
1518                         ts_cal2: calib@5e {
1519                                 reg = <0x5e 0x2>;
1520                         };
1521                 };
1522
1523                 i2c6: i2c@5c009000 {
1524                         compatible = "st,stm32f7-i2c";
1525                         reg = <0x5c009000 0x400>;
1526                         interrupt-names = "event", "error";
1527                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1528                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1529                         clocks = <&rcc I2C6_K>;
1530                         resets = <&rcc I2C6_R>;
1531                         #address-cells = <1>;
1532                         #size-cells = <0>;
1533                         status = "disabled";
1534                 };
1535
1536                 /*
1537                  * Break node order to solve dependency probe issue between
1538                  * pinctrl and exti.
1539                  */
1540                 pinctrl: pin-controller@50002000 {
1541                         #address-cells = <1>;
1542                         #size-cells = <1>;
1543                         compatible = "st,stm32mp157-pinctrl";
1544                         ranges = <0 0x50002000 0xa400>;
1545                         interrupt-parent = <&exti>;
1546                         st,syscfg = <&exti 0x60 0xff>;
1547                         hwlocks = <&hwspinlock 0>;
1548                         pins-are-numbered;
1549
1550                         gpioa: gpio@50002000 {
1551                                 gpio-controller;
1552                                 #gpio-cells = <2>;
1553                                 interrupt-controller;
1554                                 #interrupt-cells = <2>;
1555                                 reg = <0x0 0x400>;
1556                                 clocks = <&rcc GPIOA>;
1557                                 st,bank-name = "GPIOA";
1558                                 status = "disabled";
1559                         };
1560
1561                         gpiob: gpio@50003000 {
1562                                 gpio-controller;
1563                                 #gpio-cells = <2>;
1564                                 interrupt-controller;
1565                                 #interrupt-cells = <2>;
1566                                 reg = <0x1000 0x400>;
1567                                 clocks = <&rcc GPIOB>;
1568                                 st,bank-name = "GPIOB";
1569                                 status = "disabled";
1570                         };
1571
1572                         gpioc: gpio@50004000 {
1573                                 gpio-controller;
1574                                 #gpio-cells = <2>;
1575                                 interrupt-controller;
1576                                 #interrupt-cells = <2>;
1577                                 reg = <0x2000 0x400>;
1578                                 clocks = <&rcc GPIOC>;
1579                                 st,bank-name = "GPIOC";
1580                                 status = "disabled";
1581                         };
1582
1583                         gpiod: gpio@50005000 {
1584                                 gpio-controller;
1585                                 #gpio-cells = <2>;
1586                                 interrupt-controller;
1587                                 #interrupt-cells = <2>;
1588                                 reg = <0x3000 0x400>;
1589                                 clocks = <&rcc GPIOD>;
1590                                 st,bank-name = "GPIOD";
1591                                 status = "disabled";
1592                         };
1593
1594                         gpioe: gpio@50006000 {
1595                                 gpio-controller;
1596                                 #gpio-cells = <2>;
1597                                 interrupt-controller;
1598                                 #interrupt-cells = <2>;
1599                                 reg = <0x4000 0x400>;
1600                                 clocks = <&rcc GPIOE>;
1601                                 st,bank-name = "GPIOE";
1602                                 status = "disabled";
1603                         };
1604
1605                         gpiof: gpio@50007000 {
1606                                 gpio-controller;
1607                                 #gpio-cells = <2>;
1608                                 interrupt-controller;
1609                                 #interrupt-cells = <2>;
1610                                 reg = <0x5000 0x400>;
1611                                 clocks = <&rcc GPIOF>;
1612                                 st,bank-name = "GPIOF";
1613                                 status = "disabled";
1614                         };
1615
1616                         gpiog: gpio@50008000 {
1617                                 gpio-controller;
1618                                 #gpio-cells = <2>;
1619                                 interrupt-controller;
1620                                 #interrupt-cells = <2>;
1621                                 reg = <0x6000 0x400>;
1622                                 clocks = <&rcc GPIOG>;
1623                                 st,bank-name = "GPIOG";
1624                                 status = "disabled";
1625                         };
1626
1627                         gpioh: gpio@50009000 {
1628                                 gpio-controller;
1629                                 #gpio-cells = <2>;
1630                                 interrupt-controller;
1631                                 #interrupt-cells = <2>;
1632                                 reg = <0x7000 0x400>;
1633                                 clocks = <&rcc GPIOH>;
1634                                 st,bank-name = "GPIOH";
1635                                 status = "disabled";
1636                         };
1637
1638                         gpioi: gpio@5000a000 {
1639                                 gpio-controller;
1640                                 #gpio-cells = <2>;
1641                                 interrupt-controller;
1642                                 #interrupt-cells = <2>;
1643                                 reg = <0x8000 0x400>;
1644                                 clocks = <&rcc GPIOI>;
1645                                 st,bank-name = "GPIOI";
1646                                 status = "disabled";
1647                         };
1648
1649                         gpioj: gpio@5000b000 {
1650                                 gpio-controller;
1651                                 #gpio-cells = <2>;
1652                                 interrupt-controller;
1653                                 #interrupt-cells = <2>;
1654                                 reg = <0x9000 0x400>;
1655                                 clocks = <&rcc GPIOJ>;
1656                                 st,bank-name = "GPIOJ";
1657                                 status = "disabled";
1658                         };
1659
1660                         gpiok: gpio@5000c000 {
1661                                 gpio-controller;
1662                                 #gpio-cells = <2>;
1663                                 interrupt-controller;
1664                                 #interrupt-cells = <2>;
1665                                 reg = <0xa000 0x400>;
1666                                 clocks = <&rcc GPIOK>;
1667                                 st,bank-name = "GPIOK";
1668                                 status = "disabled";
1669                         };
1670                 };
1671
1672                 pinctrl_z: pin-controller-z@54004000 {
1673                         #address-cells = <1>;
1674                         #size-cells = <1>;
1675                         compatible = "st,stm32mp157-z-pinctrl";
1676                         ranges = <0 0x54004000 0x400>;
1677                         pins-are-numbered;
1678                         interrupt-parent = <&exti>;
1679                         st,syscfg = <&exti 0x60 0xff>;
1680                         hwlocks = <&hwspinlock 0>;
1681
1682                         gpioz: gpio@54004000 {
1683                                 gpio-controller;
1684                                 #gpio-cells = <2>;
1685                                 interrupt-controller;
1686                                 #interrupt-cells = <2>;
1687                                 reg = <0 0x400>;
1688                                 clocks = <&rcc GPIOZ>;
1689                                 st,bank-name = "GPIOZ";
1690                                 st,bank-ioport = <11>;
1691                                 status = "disabled";
1692                         };
1693                 };
1694         };
1695
1696         mlahb: ahb {
1697                 compatible = "st,mlahb", "simple-bus";
1698                 #address-cells = <1>;
1699                 #size-cells = <1>;
1700                 ranges;
1701                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1702                              <0x10000000 0x10000000 0x60000>,
1703                              <0x30000000 0x30000000 0x60000>;
1704
1705                 m4_rproc: m4@10000000 {
1706                         compatible = "st,stm32mp1-m4";
1707                         reg = <0x10000000 0x40000>,
1708                               <0x30000000 0x40000>,
1709                               <0x38000000 0x10000>;
1710                         resets = <&rcc MCU_R>;
1711                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1712                         st,syscfg-tz = <&rcc 0x000 0x1>;
1713                         status = "disabled";
1714                 };
1715         };
1716 };