1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
27 compatible = "arm,psci-1.0";
29 cpu_off = <0x84000002>;
30 cpu_on = <0x84000003>;
33 intc: interrupt-controller@a0021000 {
34 compatible = "arm,cortex-a7-gic";
35 #interrupt-cells = <3>;
37 reg = <0xa0021000 0x1000>,
42 compatible = "arm,armv7-timer";
43 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
46 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
47 interrupt-parent = <&intc>;
53 compatible = "fixed-clock";
54 clock-frequency = <24000000>;
59 compatible = "fixed-clock";
60 clock-frequency = <64000000>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
77 compatible = "fixed-clock";
78 clock-frequency = <4000000>;
83 cpu_thermal: cpu-thermal {
84 polling-delay-passive = <0>;
86 thermal-sensors = <&dts>;
89 cpu_alert1: cpu-alert1 {
90 temperature = <85000>;
96 temperature = <120000>;
107 booster: regulator-booster {
108 compatible = "st,stm32mp1-booster";
109 st,syscfg = <&syscfg>;
114 compatible = "syscon-reboot";
121 compatible = "simple-bus";
122 #address-cells = <1>;
124 interrupt-parent = <&intc>;
127 timers2: timer@40000000 {
128 #address-cells = <1>;
130 compatible = "st,stm32-timers";
131 reg = <0x40000000 0x400>;
132 clocks = <&rcc TIM2_K>;
134 dmas = <&dmamux1 18 0x400 0x1>,
135 <&dmamux1 19 0x400 0x1>,
136 <&dmamux1 20 0x400 0x1>,
137 <&dmamux1 21 0x400 0x1>,
138 <&dmamux1 22 0x400 0x1>;
139 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
143 compatible = "st,stm32-pwm";
149 compatible = "st,stm32h7-timer-trigger";
155 compatible = "st,stm32-timer-counter";
160 timers3: timer@40001000 {
161 #address-cells = <1>;
163 compatible = "st,stm32-timers";
164 reg = <0x40001000 0x400>;
165 clocks = <&rcc TIM3_K>;
167 dmas = <&dmamux1 23 0x400 0x1>,
168 <&dmamux1 24 0x400 0x1>,
169 <&dmamux1 25 0x400 0x1>,
170 <&dmamux1 26 0x400 0x1>,
171 <&dmamux1 27 0x400 0x1>,
172 <&dmamux1 28 0x400 0x1>;
173 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
177 compatible = "st,stm32-pwm";
183 compatible = "st,stm32h7-timer-trigger";
189 compatible = "st,stm32-timer-counter";
194 timers4: timer@40002000 {
195 #address-cells = <1>;
197 compatible = "st,stm32-timers";
198 reg = <0x40002000 0x400>;
199 clocks = <&rcc TIM4_K>;
201 dmas = <&dmamux1 29 0x400 0x1>,
202 <&dmamux1 30 0x400 0x1>,
203 <&dmamux1 31 0x400 0x1>,
204 <&dmamux1 32 0x400 0x1>;
205 dma-names = "ch1", "ch2", "ch3", "ch4";
209 compatible = "st,stm32-pwm";
215 compatible = "st,stm32h7-timer-trigger";
221 compatible = "st,stm32-timer-counter";
226 timers5: timer@40003000 {
227 #address-cells = <1>;
229 compatible = "st,stm32-timers";
230 reg = <0x40003000 0x400>;
231 clocks = <&rcc TIM5_K>;
233 dmas = <&dmamux1 55 0x400 0x1>,
234 <&dmamux1 56 0x400 0x1>,
235 <&dmamux1 57 0x400 0x1>,
236 <&dmamux1 58 0x400 0x1>,
237 <&dmamux1 59 0x400 0x1>,
238 <&dmamux1 60 0x400 0x1>;
239 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
243 compatible = "st,stm32-pwm";
249 compatible = "st,stm32h7-timer-trigger";
255 compatible = "st,stm32-timer-counter";
260 timers6: timer@40004000 {
261 #address-cells = <1>;
263 compatible = "st,stm32-timers";
264 reg = <0x40004000 0x400>;
265 clocks = <&rcc TIM6_K>;
267 dmas = <&dmamux1 69 0x400 0x1>;
272 compatible = "st,stm32h7-timer-trigger";
278 timers7: timer@40005000 {
279 #address-cells = <1>;
281 compatible = "st,stm32-timers";
282 reg = <0x40005000 0x400>;
283 clocks = <&rcc TIM7_K>;
285 dmas = <&dmamux1 70 0x400 0x1>;
290 compatible = "st,stm32h7-timer-trigger";
296 timers12: timer@40006000 {
297 #address-cells = <1>;
299 compatible = "st,stm32-timers";
300 reg = <0x40006000 0x400>;
301 clocks = <&rcc TIM12_K>;
306 compatible = "st,stm32-pwm";
312 compatible = "st,stm32h7-timer-trigger";
318 timers13: timer@40007000 {
319 #address-cells = <1>;
321 compatible = "st,stm32-timers";
322 reg = <0x40007000 0x400>;
323 clocks = <&rcc TIM13_K>;
328 compatible = "st,stm32-pwm";
334 compatible = "st,stm32h7-timer-trigger";
340 timers14: timer@40008000 {
341 #address-cells = <1>;
343 compatible = "st,stm32-timers";
344 reg = <0x40008000 0x400>;
345 clocks = <&rcc TIM14_K>;
350 compatible = "st,stm32-pwm";
356 compatible = "st,stm32h7-timer-trigger";
362 lptimer1: timer@40009000 {
363 #address-cells = <1>;
365 compatible = "st,stm32-lptimer";
366 reg = <0x40009000 0x400>;
367 clocks = <&rcc LPTIM1_K>;
372 compatible = "st,stm32-pwm-lp";
378 compatible = "st,stm32-lptimer-trigger";
384 compatible = "st,stm32-lptimer-counter";
390 #address-cells = <1>;
392 compatible = "st,stm32h7-spi";
393 reg = <0x4000b000 0x400>;
394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&rcc SPI2_K>;
396 resets = <&rcc SPI2_R>;
397 dmas = <&dmamux1 39 0x400 0x05>,
398 <&dmamux1 40 0x400 0x05>;
399 dma-names = "rx", "tx";
403 i2s2: audio-controller@4000b000 {
404 compatible = "st,stm32h7-i2s";
405 #sound-dai-cells = <0>;
406 reg = <0x4000b000 0x400>;
407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
408 dmas = <&dmamux1 39 0x400 0x01>,
409 <&dmamux1 40 0x400 0x01>;
410 dma-names = "rx", "tx";
415 #address-cells = <1>;
417 compatible = "st,stm32h7-spi";
418 reg = <0x4000c000 0x400>;
419 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&rcc SPI3_K>;
421 resets = <&rcc SPI3_R>;
422 dmas = <&dmamux1 61 0x400 0x05>,
423 <&dmamux1 62 0x400 0x05>;
424 dma-names = "rx", "tx";
428 i2s3: audio-controller@4000c000 {
429 compatible = "st,stm32h7-i2s";
430 #sound-dai-cells = <0>;
431 reg = <0x4000c000 0x400>;
432 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
433 dmas = <&dmamux1 61 0x400 0x01>,
434 <&dmamux1 62 0x400 0x01>;
435 dma-names = "rx", "tx";
439 spdifrx: audio-controller@4000d000 {
440 compatible = "st,stm32h7-spdifrx";
441 #sound-dai-cells = <0>;
442 reg = <0x4000d000 0x400>;
443 clocks = <&rcc SPDIF_K>;
444 clock-names = "kclk";
445 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
446 dmas = <&dmamux1 93 0x400 0x01>,
447 <&dmamux1 94 0x400 0x01>;
448 dma-names = "rx", "rx-ctrl";
452 usart2: serial@4000e000 {
453 compatible = "st,stm32h7-uart";
454 reg = <0x4000e000 0x400>;
455 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&rcc USART2_K>;
460 usart3: serial@4000f000 {
461 compatible = "st,stm32h7-uart";
462 reg = <0x4000f000 0x400>;
463 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&rcc USART3_K>;
468 uart4: serial@40010000 {
469 compatible = "st,stm32h7-uart";
470 reg = <0x40010000 0x400>;
471 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&rcc UART4_K>;
476 uart5: serial@40011000 {
477 compatible = "st,stm32h7-uart";
478 reg = <0x40011000 0x400>;
479 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&rcc UART5_K>;
485 compatible = "st,stm32f7-i2c";
486 reg = <0x40012000 0x400>;
487 interrupt-names = "event", "error";
488 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&rcc I2C1_K>;
491 resets = <&rcc I2C1_R>;
492 #address-cells = <1>;
499 compatible = "st,stm32f7-i2c";
500 reg = <0x40013000 0x400>;
501 interrupt-names = "event", "error";
502 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&rcc I2C2_K>;
505 resets = <&rcc I2C2_R>;
506 #address-cells = <1>;
513 compatible = "st,stm32f7-i2c";
514 reg = <0x40014000 0x400>;
515 interrupt-names = "event", "error";
516 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&rcc I2C3_K>;
519 resets = <&rcc I2C3_R>;
520 #address-cells = <1>;
527 compatible = "st,stm32f7-i2c";
528 reg = <0x40015000 0x400>;
529 interrupt-names = "event", "error";
530 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&rcc I2C5_K>;
533 resets = <&rcc I2C5_R>;
534 #address-cells = <1>;
541 compatible = "st,stm32-cec";
542 reg = <0x40016000 0x400>;
543 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&rcc CEC_K>, <&clk_lse>;
545 clock-names = "cec", "hdmi-cec";
550 compatible = "st,stm32h7-dac-core";
551 reg = <0x40017000 0x400>;
552 clocks = <&rcc DAC12>;
553 clock-names = "pclk";
554 #address-cells = <1>;
559 compatible = "st,stm32-dac";
560 #io-channels-cells = <1>;
566 compatible = "st,stm32-dac";
567 #io-channels-cells = <1>;
573 uart7: serial@40018000 {
574 compatible = "st,stm32h7-uart";
575 reg = <0x40018000 0x400>;
576 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&rcc UART7_K>;
581 uart8: serial@40019000 {
582 compatible = "st,stm32h7-uart";
583 reg = <0x40019000 0x400>;
584 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&rcc UART8_K>;
589 timers1: timer@44000000 {
590 #address-cells = <1>;
592 compatible = "st,stm32-timers";
593 reg = <0x44000000 0x400>;
594 clocks = <&rcc TIM1_K>;
596 dmas = <&dmamux1 11 0x400 0x1>,
597 <&dmamux1 12 0x400 0x1>,
598 <&dmamux1 13 0x400 0x1>,
599 <&dmamux1 14 0x400 0x1>,
600 <&dmamux1 15 0x400 0x1>,
601 <&dmamux1 16 0x400 0x1>,
602 <&dmamux1 17 0x400 0x1>;
603 dma-names = "ch1", "ch2", "ch3", "ch4",
608 compatible = "st,stm32-pwm";
614 compatible = "st,stm32h7-timer-trigger";
620 compatible = "st,stm32-timer-counter";
625 timers8: timer@44001000 {
626 #address-cells = <1>;
628 compatible = "st,stm32-timers";
629 reg = <0x44001000 0x400>;
630 clocks = <&rcc TIM8_K>;
632 dmas = <&dmamux1 47 0x400 0x1>,
633 <&dmamux1 48 0x400 0x1>,
634 <&dmamux1 49 0x400 0x1>,
635 <&dmamux1 50 0x400 0x1>,
636 <&dmamux1 51 0x400 0x1>,
637 <&dmamux1 52 0x400 0x1>,
638 <&dmamux1 53 0x400 0x1>;
639 dma-names = "ch1", "ch2", "ch3", "ch4",
644 compatible = "st,stm32-pwm";
650 compatible = "st,stm32h7-timer-trigger";
656 compatible = "st,stm32-timer-counter";
661 usart6: serial@44003000 {
662 compatible = "st,stm32h7-uart";
663 reg = <0x44003000 0x400>;
664 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&rcc USART6_K>;
670 #address-cells = <1>;
672 compatible = "st,stm32h7-spi";
673 reg = <0x44004000 0x400>;
674 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&rcc SPI1_K>;
676 resets = <&rcc SPI1_R>;
677 dmas = <&dmamux1 37 0x400 0x05>,
678 <&dmamux1 38 0x400 0x05>;
679 dma-names = "rx", "tx";
683 i2s1: audio-controller@44004000 {
684 compatible = "st,stm32h7-i2s";
685 #sound-dai-cells = <0>;
686 reg = <0x44004000 0x400>;
687 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
688 dmas = <&dmamux1 37 0x400 0x01>,
689 <&dmamux1 38 0x400 0x01>;
690 dma-names = "rx", "tx";
695 #address-cells = <1>;
697 compatible = "st,stm32h7-spi";
698 reg = <0x44005000 0x400>;
699 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&rcc SPI4_K>;
701 resets = <&rcc SPI4_R>;
702 dmas = <&dmamux1 83 0x400 0x05>,
703 <&dmamux1 84 0x400 0x05>;
704 dma-names = "rx", "tx";
708 timers15: timer@44006000 {
709 #address-cells = <1>;
711 compatible = "st,stm32-timers";
712 reg = <0x44006000 0x400>;
713 clocks = <&rcc TIM15_K>;
715 dmas = <&dmamux1 105 0x400 0x1>,
716 <&dmamux1 106 0x400 0x1>,
717 <&dmamux1 107 0x400 0x1>,
718 <&dmamux1 108 0x400 0x1>;
719 dma-names = "ch1", "up", "trig", "com";
723 compatible = "st,stm32-pwm";
729 compatible = "st,stm32h7-timer-trigger";
735 timers16: timer@44007000 {
736 #address-cells = <1>;
738 compatible = "st,stm32-timers";
739 reg = <0x44007000 0x400>;
740 clocks = <&rcc TIM16_K>;
742 dmas = <&dmamux1 109 0x400 0x1>,
743 <&dmamux1 110 0x400 0x1>;
744 dma-names = "ch1", "up";
748 compatible = "st,stm32-pwm";
753 compatible = "st,stm32h7-timer-trigger";
759 timers17: timer@44008000 {
760 #address-cells = <1>;
762 compatible = "st,stm32-timers";
763 reg = <0x44008000 0x400>;
764 clocks = <&rcc TIM17_K>;
766 dmas = <&dmamux1 111 0x400 0x1>,
767 <&dmamux1 112 0x400 0x1>;
768 dma-names = "ch1", "up";
772 compatible = "st,stm32-pwm";
778 compatible = "st,stm32h7-timer-trigger";
785 #address-cells = <1>;
787 compatible = "st,stm32h7-spi";
788 reg = <0x44009000 0x400>;
789 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&rcc SPI5_K>;
791 resets = <&rcc SPI5_R>;
792 dmas = <&dmamux1 85 0x400 0x05>,
793 <&dmamux1 86 0x400 0x05>;
794 dma-names = "rx", "tx";
799 compatible = "st,stm32h7-sai";
800 #address-cells = <1>;
802 ranges = <0 0x4400a000 0x400>;
803 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
804 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
805 resets = <&rcc SAI1_R>;
808 sai1a: audio-controller@4400a004 {
809 #sound-dai-cells = <0>;
811 compatible = "st,stm32-sai-sub-a";
813 clocks = <&rcc SAI1_K>;
814 clock-names = "sai_ck";
815 dmas = <&dmamux1 87 0x400 0x01>;
819 sai1b: audio-controller@4400a024 {
820 #sound-dai-cells = <0>;
821 compatible = "st,stm32-sai-sub-b";
823 clocks = <&rcc SAI1_K>;
824 clock-names = "sai_ck";
825 dmas = <&dmamux1 88 0x400 0x01>;
831 compatible = "st,stm32h7-sai";
832 #address-cells = <1>;
834 ranges = <0 0x4400b000 0x400>;
835 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
836 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
837 resets = <&rcc SAI2_R>;
840 sai2a: audio-controller@4400b004 {
841 #sound-dai-cells = <0>;
842 compatible = "st,stm32-sai-sub-a";
844 clocks = <&rcc SAI2_K>;
845 clock-names = "sai_ck";
846 dmas = <&dmamux1 89 0x400 0x01>;
850 sai2b: audio-controller@4400b024 {
851 #sound-dai-cells = <0>;
852 compatible = "st,stm32-sai-sub-b";
854 clocks = <&rcc SAI2_K>;
855 clock-names = "sai_ck";
856 dmas = <&dmamux1 90 0x400 0x01>;
862 compatible = "st,stm32h7-sai";
863 #address-cells = <1>;
865 ranges = <0 0x4400c000 0x400>;
866 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
867 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
868 resets = <&rcc SAI3_R>;
871 sai3a: audio-controller@4400c004 {
872 #sound-dai-cells = <0>;
873 compatible = "st,stm32-sai-sub-a";
875 clocks = <&rcc SAI3_K>;
876 clock-names = "sai_ck";
877 dmas = <&dmamux1 113 0x400 0x01>;
881 sai3b: audio-controller@4400c024 {
882 #sound-dai-cells = <0>;
883 compatible = "st,stm32-sai-sub-b";
885 clocks = <&rcc SAI3_K>;
886 clock-names = "sai_ck";
887 dmas = <&dmamux1 114 0x400 0x01>;
892 dfsdm: dfsdm@4400d000 {
893 compatible = "st,stm32mp1-dfsdm";
894 reg = <0x4400d000 0x800>;
895 clocks = <&rcc DFSDM_K>;
896 clock-names = "dfsdm";
897 #address-cells = <1>;
902 compatible = "st,stm32-dfsdm-adc";
903 #io-channel-cells = <1>;
905 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
906 dmas = <&dmamux1 101 0x400 0x01>;
912 compatible = "st,stm32-dfsdm-adc";
913 #io-channel-cells = <1>;
915 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
916 dmas = <&dmamux1 102 0x400 0x01>;
922 compatible = "st,stm32-dfsdm-adc";
923 #io-channel-cells = <1>;
925 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
926 dmas = <&dmamux1 103 0x400 0x01>;
932 compatible = "st,stm32-dfsdm-adc";
933 #io-channel-cells = <1>;
935 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
936 dmas = <&dmamux1 104 0x400 0x01>;
942 compatible = "st,stm32-dfsdm-adc";
943 #io-channel-cells = <1>;
945 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
946 dmas = <&dmamux1 91 0x400 0x01>;
952 compatible = "st,stm32-dfsdm-adc";
953 #io-channel-cells = <1>;
955 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
956 dmas = <&dmamux1 92 0x400 0x01>;
962 dma1: dma-controller@48000000 {
963 compatible = "st,stm32-dma";
964 reg = <0x48000000 0x400>;
965 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&rcc DMA1>;
974 resets = <&rcc DMA1_R>;
980 dma2: dma-controller@48001000 {
981 compatible = "st,stm32-dma";
982 reg = <0x48001000 0x400>;
983 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&rcc DMA2>;
992 resets = <&rcc DMA2_R>;
998 dmamux1: dma-router@48002000 {
999 compatible = "st,stm32h7-dmamux";
1000 reg = <0x48002000 0x1c>;
1002 dma-requests = <128>;
1003 dma-masters = <&dma1 &dma2>;
1004 dma-channels = <16>;
1005 clocks = <&rcc DMAMUX>;
1006 resets = <&rcc DMAMUX_R>;
1010 compatible = "st,stm32mp1-adc-core";
1011 reg = <0x48003000 0x400>;
1012 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1013 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1015 clock-names = "bus", "adc";
1016 interrupt-controller;
1017 st,syscfg = <&syscfg>;
1018 #interrupt-cells = <1>;
1019 #address-cells = <1>;
1021 status = "disabled";
1024 compatible = "st,stm32mp1-adc";
1025 #io-channel-cells = <1>;
1027 interrupt-parent = <&adc>;
1029 dmas = <&dmamux1 9 0x400 0x01>;
1031 status = "disabled";
1035 compatible = "st,stm32mp1-adc";
1036 #io-channel-cells = <1>;
1038 interrupt-parent = <&adc>;
1040 dmas = <&dmamux1 10 0x400 0x01>;
1042 status = "disabled";
1046 sdmmc3: sdmmc@48004000 {
1047 compatible = "arm,pl18x", "arm,primecell";
1048 arm,primecell-periphid = <0x10153180>;
1049 reg = <0x48004000 0x400>;
1050 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1051 interrupt-names = "cmd_irq";
1052 clocks = <&rcc SDMMC3_K>;
1053 clock-names = "apb_pclk";
1054 resets = <&rcc SDMMC3_R>;
1057 max-frequency = <120000000>;
1058 status = "disabled";
1061 usbotg_hs: usb-otg@49000000 {
1062 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1063 reg = <0x49000000 0x10000>;
1064 clocks = <&rcc USBO_K>;
1065 clock-names = "otg";
1066 resets = <&rcc USBO_R>;
1067 reset-names = "dwc2";
1068 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1069 g-rx-fifo-size = <256>;
1070 g-np-tx-fifo-size = <32>;
1071 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1073 usb33d-supply = <&usb33>;
1074 status = "disabled";
1077 hwspinlock: hwspinlock@4c000000 {
1078 compatible = "st,stm32-hwspinlock";
1079 #hwlock-cells = <1>;
1080 reg = <0x4c000000 0x400>;
1081 clocks = <&rcc HSEM>;
1082 clock-names = "hwspinlock";
1085 ipcc: mailbox@4c001000 {
1086 compatible = "st,stm32mp1-ipcc";
1088 reg = <0x4c001000 0x400>;
1090 interrupts-extended =
1091 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1092 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1094 interrupt-names = "rx", "tx", "wakeup";
1095 clocks = <&rcc IPCC>;
1097 status = "disabled";
1100 dcmi: dcmi@4c006000 {
1101 compatible = "st,stm32-dcmi";
1102 reg = <0x4c006000 0x400>;
1103 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1104 resets = <&rcc CAMITF_R>;
1105 clocks = <&rcc DCMI>;
1106 clock-names = "mclk";
1107 dmas = <&dmamux1 75 0x400 0x0d>;
1109 status = "disabled";
1113 compatible = "st,stm32mp1-rcc", "syscon";
1114 reg = <0x50000000 0x1000>;
1119 pwr_regulators: pwr@50001000 {
1120 compatible = "st,stm32mp1,pwr-reg";
1121 reg = <0x50001000 0x10>;
1124 regulator-name = "reg11";
1125 regulator-min-microvolt = <1100000>;
1126 regulator-max-microvolt = <1100000>;
1130 regulator-name = "reg18";
1131 regulator-min-microvolt = <1800000>;
1132 regulator-max-microvolt = <1800000>;
1136 regulator-name = "usb33";
1137 regulator-min-microvolt = <3300000>;
1138 regulator-max-microvolt = <3300000>;
1142 exti: interrupt-controller@5000d000 {
1143 compatible = "st,stm32mp1-exti", "syscon";
1144 interrupt-controller;
1145 #interrupt-cells = <2>;
1146 reg = <0x5000d000 0x400>;
1149 syscfg: syscon@50020000 {
1150 compatible = "st,stm32mp157-syscfg", "syscon";
1151 reg = <0x50020000 0x400>;
1152 clocks = <&rcc SYSCFG>;
1155 lptimer2: timer@50021000 {
1156 #address-cells = <1>;
1158 compatible = "st,stm32-lptimer";
1159 reg = <0x50021000 0x400>;
1160 clocks = <&rcc LPTIM2_K>;
1161 clock-names = "mux";
1162 status = "disabled";
1165 compatible = "st,stm32-pwm-lp";
1167 status = "disabled";
1171 compatible = "st,stm32-lptimer-trigger";
1173 status = "disabled";
1177 compatible = "st,stm32-lptimer-counter";
1178 status = "disabled";
1182 lptimer3: timer@50022000 {
1183 #address-cells = <1>;
1185 compatible = "st,stm32-lptimer";
1186 reg = <0x50022000 0x400>;
1187 clocks = <&rcc LPTIM3_K>;
1188 clock-names = "mux";
1189 status = "disabled";
1192 compatible = "st,stm32-pwm-lp";
1194 status = "disabled";
1198 compatible = "st,stm32-lptimer-trigger";
1200 status = "disabled";
1204 lptimer4: timer@50023000 {
1205 compatible = "st,stm32-lptimer";
1206 reg = <0x50023000 0x400>;
1207 clocks = <&rcc LPTIM4_K>;
1208 clock-names = "mux";
1209 status = "disabled";
1212 compatible = "st,stm32-pwm-lp";
1214 status = "disabled";
1218 lptimer5: timer@50024000 {
1219 compatible = "st,stm32-lptimer";
1220 reg = <0x50024000 0x400>;
1221 clocks = <&rcc LPTIM5_K>;
1222 clock-names = "mux";
1223 status = "disabled";
1226 compatible = "st,stm32-pwm-lp";
1228 status = "disabled";
1232 vrefbuf: vrefbuf@50025000 {
1233 compatible = "st,stm32-vrefbuf";
1234 reg = <0x50025000 0x8>;
1235 regulator-min-microvolt = <1500000>;
1236 regulator-max-microvolt = <2500000>;
1237 clocks = <&rcc VREF>;
1238 status = "disabled";
1241 sai4: sai@50027000 {
1242 compatible = "st,stm32h7-sai";
1243 #address-cells = <1>;
1245 ranges = <0 0x50027000 0x400>;
1246 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1247 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1248 resets = <&rcc SAI4_R>;
1249 status = "disabled";
1251 sai4a: audio-controller@50027004 {
1252 #sound-dai-cells = <0>;
1253 compatible = "st,stm32-sai-sub-a";
1255 clocks = <&rcc SAI4_K>;
1256 clock-names = "sai_ck";
1257 dmas = <&dmamux1 99 0x400 0x01>;
1258 status = "disabled";
1261 sai4b: audio-controller@50027024 {
1262 #sound-dai-cells = <0>;
1263 compatible = "st,stm32-sai-sub-b";
1265 clocks = <&rcc SAI4_K>;
1266 clock-names = "sai_ck";
1267 dmas = <&dmamux1 100 0x400 0x01>;
1268 status = "disabled";
1272 dts: thermal@50028000 {
1273 compatible = "st,stm32-thermal";
1274 reg = <0x50028000 0x100>;
1275 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1276 clocks = <&rcc TMPSENS>;
1277 clock-names = "pclk";
1278 #thermal-sensor-cells = <0>;
1279 status = "disabled";
1282 hash1: hash@54002000 {
1283 compatible = "st,stm32f756-hash";
1284 reg = <0x54002000 0x400>;
1285 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1286 clocks = <&rcc HASH1>;
1287 resets = <&rcc HASH1_R>;
1288 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1291 status = "disabled";
1294 rng1: rng@54003000 {
1295 compatible = "st,stm32-rng";
1296 reg = <0x54003000 0x400>;
1297 clocks = <&rcc RNG1_K>;
1298 resets = <&rcc RNG1_R>;
1299 status = "disabled";
1302 mdma1: dma-controller@58000000 {
1303 compatible = "st,stm32h7-mdma";
1304 reg = <0x58000000 0x1000>;
1305 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1306 clocks = <&rcc MDMA>;
1307 resets = <&rcc MDMA_R>;
1309 dma-channels = <32>;
1310 dma-requests = <48>;
1313 fmc: nand-controller@58002000 {
1314 compatible = "st,stm32mp15-fmc2";
1315 reg = <0x58002000 0x1000>,
1316 <0x80000000 0x1000>,
1317 <0x88010000 0x1000>,
1318 <0x88020000 0x1000>,
1319 <0x81000000 0x1000>,
1320 <0x89010000 0x1000>,
1321 <0x89020000 0x1000>;
1322 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1323 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1324 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1325 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1326 dma-names = "tx", "rx", "ecc";
1327 clocks = <&rcc FMC_K>;
1328 resets = <&rcc FMC_R>;
1329 status = "disabled";
1332 qspi: spi@58003000 {
1333 compatible = "st,stm32f469-qspi";
1334 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1335 reg-names = "qspi", "qspi_mm";
1336 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1337 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1338 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1339 dma-names = "tx", "rx";
1340 clocks = <&rcc QSPI_K>;
1341 resets = <&rcc QSPI_R>;
1342 status = "disabled";
1345 sdmmc1: sdmmc@58005000 {
1346 compatible = "arm,pl18x", "arm,primecell";
1347 arm,primecell-periphid = <0x10153180>;
1348 reg = <0x58005000 0x1000>;
1349 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-names = "cmd_irq";
1351 clocks = <&rcc SDMMC1_K>;
1352 clock-names = "apb_pclk";
1353 resets = <&rcc SDMMC1_R>;
1356 max-frequency = <120000000>;
1357 status = "disabled";
1360 sdmmc2: sdmmc@58007000 {
1361 compatible = "arm,pl18x", "arm,primecell";
1362 arm,primecell-periphid = <0x10153180>;
1363 reg = <0x58007000 0x1000>;
1364 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1365 interrupt-names = "cmd_irq";
1366 clocks = <&rcc SDMMC2_K>;
1367 clock-names = "apb_pclk";
1368 resets = <&rcc SDMMC2_R>;
1371 max-frequency = <120000000>;
1372 status = "disabled";
1375 crc1: crc@58009000 {
1376 compatible = "st,stm32f7-crc";
1377 reg = <0x58009000 0x400>;
1378 clocks = <&rcc CRC1>;
1379 status = "disabled";
1382 stmmac_axi_config_0: stmmac-axi-config {
1383 snps,wr_osr_lmt = <0x7>;
1384 snps,rd_osr_lmt = <0x7>;
1385 snps,blen = <0 0 0 0 16 8 4>;
1388 ethernet0: ethernet@5800a000 {
1389 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1390 reg = <0x5800a000 0x2000>;
1391 reg-names = "stmmaceth";
1392 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1393 interrupt-names = "macirq";
1394 clock-names = "stmmaceth",
1400 clocks = <&rcc ETHMAC>,
1406 st,syscon = <&syscfg 0x4>;
1409 snps,en-tx-lpi-clockgating;
1410 snps,axi-config = <&stmmac_axi_config_0>;
1412 status = "disabled";
1415 usbh_ohci: usbh-ohci@5800c000 {
1416 compatible = "generic-ohci";
1417 reg = <0x5800c000 0x1000>;
1418 clocks = <&rcc USBH>;
1419 resets = <&rcc USBH_R>;
1420 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1421 status = "disabled";
1424 usbh_ehci: usbh-ehci@5800d000 {
1425 compatible = "generic-ehci";
1426 reg = <0x5800d000 0x1000>;
1427 clocks = <&rcc USBH>;
1428 resets = <&rcc USBH_R>;
1429 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1430 companion = <&usbh_ohci>;
1431 status = "disabled";
1434 ltdc: display-controller@5a001000 {
1435 compatible = "st,stm32-ltdc";
1436 reg = <0x5a001000 0x400>;
1437 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1439 clocks = <&rcc LTDC_PX>;
1440 clock-names = "lcd";
1441 resets = <&rcc LTDC_R>;
1442 status = "disabled";
1445 iwdg2: watchdog@5a002000 {
1446 compatible = "st,stm32mp1-iwdg";
1447 reg = <0x5a002000 0x400>;
1448 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1449 clock-names = "pclk", "lsi";
1450 status = "disabled";
1453 usbphyc: usbphyc@5a006000 {
1454 #address-cells = <1>;
1456 compatible = "st,stm32mp1-usbphyc";
1457 reg = <0x5a006000 0x1000>;
1458 clocks = <&rcc USBPHY_K>;
1459 resets = <&rcc USBPHY_R>;
1460 vdda1v1-supply = <®11>;
1461 vdda1v8-supply = <®18>;
1462 status = "disabled";
1464 usbphyc_port0: usb-phy@0 {
1469 usbphyc_port1: usb-phy@1 {
1475 usart1: serial@5c000000 {
1476 compatible = "st,stm32h7-uart";
1477 reg = <0x5c000000 0x400>;
1478 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&rcc USART1_K>;
1480 status = "disabled";
1483 spi6: spi@5c001000 {
1484 #address-cells = <1>;
1486 compatible = "st,stm32h7-spi";
1487 reg = <0x5c001000 0x400>;
1488 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1489 clocks = <&rcc SPI6_K>;
1490 resets = <&rcc SPI6_R>;
1491 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1492 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1493 dma-names = "rx", "tx";
1494 status = "disabled";
1497 i2c4: i2c@5c002000 {
1498 compatible = "st,stm32f7-i2c";
1499 reg = <0x5c002000 0x400>;
1500 interrupt-names = "event", "error";
1501 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1503 clocks = <&rcc I2C4_K>;
1504 resets = <&rcc I2C4_R>;
1505 #address-cells = <1>;
1508 status = "disabled";
1512 compatible = "st,stm32mp1-rtc";
1513 reg = <0x5c004000 0x400>;
1514 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1515 clock-names = "pclk", "rtc_ck";
1516 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1517 status = "disabled";
1520 bsec: efuse@5c005000 {
1521 compatible = "st,stm32mp15-bsec";
1522 reg = <0x5c005000 0x400>;
1523 #address-cells = <1>;
1533 i2c6: i2c@5c009000 {
1534 compatible = "st,stm32f7-i2c";
1535 reg = <0x5c009000 0x400>;
1536 interrupt-names = "event", "error";
1537 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1539 clocks = <&rcc I2C6_K>;
1540 resets = <&rcc I2C6_R>;
1541 #address-cells = <1>;
1544 status = "disabled";
1548 * Break node order to solve dependency probe issue between
1551 pinctrl: pin-controller@50002000 {
1552 #address-cells = <1>;
1554 compatible = "st,stm32mp157-pinctrl";
1555 ranges = <0 0x50002000 0xa400>;
1556 interrupt-parent = <&exti>;
1557 st,syscfg = <&exti 0x60 0xff>;
1558 hwlocks = <&hwspinlock 0>;
1561 gpioa: gpio@50002000 {
1564 interrupt-controller;
1565 #interrupt-cells = <2>;
1567 clocks = <&rcc GPIOA>;
1568 st,bank-name = "GPIOA";
1569 status = "disabled";
1572 gpiob: gpio@50003000 {
1575 interrupt-controller;
1576 #interrupt-cells = <2>;
1577 reg = <0x1000 0x400>;
1578 clocks = <&rcc GPIOB>;
1579 st,bank-name = "GPIOB";
1580 status = "disabled";
1583 gpioc: gpio@50004000 {
1586 interrupt-controller;
1587 #interrupt-cells = <2>;
1588 reg = <0x2000 0x400>;
1589 clocks = <&rcc GPIOC>;
1590 st,bank-name = "GPIOC";
1591 status = "disabled";
1594 gpiod: gpio@50005000 {
1597 interrupt-controller;
1598 #interrupt-cells = <2>;
1599 reg = <0x3000 0x400>;
1600 clocks = <&rcc GPIOD>;
1601 st,bank-name = "GPIOD";
1602 status = "disabled";
1605 gpioe: gpio@50006000 {
1608 interrupt-controller;
1609 #interrupt-cells = <2>;
1610 reg = <0x4000 0x400>;
1611 clocks = <&rcc GPIOE>;
1612 st,bank-name = "GPIOE";
1613 status = "disabled";
1616 gpiof: gpio@50007000 {
1619 interrupt-controller;
1620 #interrupt-cells = <2>;
1621 reg = <0x5000 0x400>;
1622 clocks = <&rcc GPIOF>;
1623 st,bank-name = "GPIOF";
1624 status = "disabled";
1627 gpiog: gpio@50008000 {
1630 interrupt-controller;
1631 #interrupt-cells = <2>;
1632 reg = <0x6000 0x400>;
1633 clocks = <&rcc GPIOG>;
1634 st,bank-name = "GPIOG";
1635 status = "disabled";
1638 gpioh: gpio@50009000 {
1641 interrupt-controller;
1642 #interrupt-cells = <2>;
1643 reg = <0x7000 0x400>;
1644 clocks = <&rcc GPIOH>;
1645 st,bank-name = "GPIOH";
1646 status = "disabled";
1649 gpioi: gpio@5000a000 {
1652 interrupt-controller;
1653 #interrupt-cells = <2>;
1654 reg = <0x8000 0x400>;
1655 clocks = <&rcc GPIOI>;
1656 st,bank-name = "GPIOI";
1657 status = "disabled";
1660 gpioj: gpio@5000b000 {
1663 interrupt-controller;
1664 #interrupt-cells = <2>;
1665 reg = <0x9000 0x400>;
1666 clocks = <&rcc GPIOJ>;
1667 st,bank-name = "GPIOJ";
1668 status = "disabled";
1671 gpiok: gpio@5000c000 {
1674 interrupt-controller;
1675 #interrupt-cells = <2>;
1676 reg = <0xa000 0x400>;
1677 clocks = <&rcc GPIOK>;
1678 st,bank-name = "GPIOK";
1679 status = "disabled";
1683 pinctrl_z: pin-controller-z@54004000 {
1684 #address-cells = <1>;
1686 compatible = "st,stm32mp157-z-pinctrl";
1687 ranges = <0 0x54004000 0x400>;
1689 interrupt-parent = <&exti>;
1690 st,syscfg = <&exti 0x60 0xff>;
1691 hwlocks = <&hwspinlock 0>;
1693 gpioz: gpio@54004000 {
1696 interrupt-controller;
1697 #interrupt-cells = <2>;
1699 clocks = <&rcc GPIOZ>;
1700 st,bank-name = "GPIOZ";
1701 st,bank-ioport = <11>;
1702 status = "disabled";
1708 compatible = "st,mlahb", "simple-bus";
1709 #address-cells = <1>;
1712 dma-ranges = <0x00000000 0x38000000 0x10000>,
1713 <0x10000000 0x10000000 0x60000>,
1714 <0x30000000 0x30000000 0x60000>;
1716 m4_rproc: m4@10000000 {
1717 compatible = "st,stm32mp1-m4";
1718 reg = <0x10000000 0x40000>,
1719 <0x30000000 0x40000>,
1720 <0x38000000 0x10000>;
1721 resets = <&rcc MCU_R>;
1722 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1723 st,syscfg-tz = <&rcc 0x000 0x1>;
1724 status = "disabled";