arch/arm/dts/stm32h743-pinctrl.dtsi

   1 /*
   2  * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
  44
  45 / {
  46         soc {
  47                 pin-controller {
  48                         #address-cells = <1>;
  49                         #size-cells = <1>;
  50                         compatible = "st,stm32h743-pinctrl";
  51                         ranges = <0 0x58020000 0x3000>;
  52                         pins-are-numbered;
  53
  54                         gpioa: gpio@58020000 {
  55                                 gpio-controller;
  56                                 #gpio-cells = <2>;
  57                                 compatible = "st,stm32-gpio";
  58                                 reg = <0x0 0x400>;
  59                                 clocks = <&rcc GPIOA_CK>;
  60                                 st,bank-name = "GPIOA";
  61                         };
  62
  63                         gpiob: gpio@58020400 {
  64                                 gpio-controller;
  65                                 #gpio-cells = <2>;
  66                                 compatible = "st,stm32-gpio";
  67                                 reg = <0x400 0x400>;
  68                                 clocks = <&rcc GPIOB_CK>;
  69                                 st,bank-name = "GPIOB";
  70                         };
  71
  72                         gpioc: gpio@58020800 {
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                                 compatible = "st,stm32-gpio";
  76                                 reg = <0x800 0x400>;
  77                                 clocks = <&rcc GPIOC_CK>;
  78                                 st,bank-name = "GPIOC";
  79                         };
  80
  81                         gpiod: gpio@58020c00 {
  82                                 gpio-controller;
  83                                 #gpio-cells = <2>;
  84                                 compatible = "st,stm32-gpio";
  85                                 reg = <0xc00 0x400>;
  86                                 clocks = <&rcc GPIOD_CK>;
  87                                 st,bank-name = "GPIOD";
  88                         };
  89
  90                         gpioe: gpio@58021000 {
  91                                 gpio-controller;
  92                                 #gpio-cells = <2>;
  93                                 compatible = "st,stm32-gpio";
  94                                 reg = <0x1000 0x400>;
  95                                 clocks = <&rcc GPIOE_CK>;
  96                                 st,bank-name = "GPIOE";
  97                         };
  98
  99                         gpiof: gpio@58021400 {
 100                                 gpio-controller;
 101                                 #gpio-cells = <2>;
 102                                 compatible = "st,stm32-gpio";
 103                                 reg = <0x1400 0x400>;
 104                                 clocks = <&rcc GPIOF_CK>;
 105                                 st,bank-name = "GPIOF";
 106                         };
 107
 108                         gpiog: gpio@58021800 {
 109                                 gpio-controller;
 110                                 #gpio-cells = <2>;
 111                                 compatible = "st,stm32-gpio";
 112                                 reg = <0x1800 0x400>;
 113                                 clocks = <&rcc GPIOG_CK>;
 114                                 st,bank-name = "GPIOG";
 115                         };
 116
 117                         gpioh: gpio@58021c00 {
 118                                 gpio-controller;
 119                                 #gpio-cells = <2>;
 120                                 compatible = "st,stm32-gpio";
 121                                 reg = <0x1c00 0x400>;
 122                                 clocks = <&rcc GPIOH_CK>;
 123                                 st,bank-name = "GPIOH";
 124                         };
 125
 126                         gpioi: gpio@58022000 {
 127                                 gpio-controller;
 128                                 #gpio-cells = <2>;
 129                                 compatible = "st,stm32-gpio";
 130                                 reg = <0x2000 0x400>;
 131                                 clocks = <&rcc GPIOI_CK>;
 132                                 st,bank-name = "GPIOI";
 133                         };
 134
 135                         gpioj: gpio@58022400 {
 136                                 gpio-controller;
 137                                 #gpio-cells = <2>;
 138                                 compatible = "st,stm32-gpio";
 139                                 reg = <0x2400 0x400>;
 140                                 clocks = <&rcc GPIOJ_CK>;
 141                                 st,bank-name = "GPIOJ";
 142                         };
 143
 144                         gpiok: gpio@58022800 {
 145                                 gpio-controller;
 146                                 #gpio-cells = <2>;
 147                                 compatible = "st,stm32-gpio";
 148                                 reg = <0x2800 0x400>;
 149                                 clocks = <&rcc GPIOK_CK>;
 150                                 st,bank-name = "GPIOK";
 151                         };
 152
 153                         usart1_pins: usart1@0 {
 154                                 pins1 {
 155                                         pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
 156                                         bias-disable;
 157                                         drive-push-pull;
 158                                         slew-rate = <0>;
 159                                 };
 160                                 pins2 {
 161                                         pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
 162                                         bias-disable;
 163                                 };
 164                         };
 165
 166                         usart2_pins: usart2@0 {
 167                                 pins1 {
 168                                         pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
 169                                         bias-disable;
 170                                         drive-push-pull;
 171                                         slew-rate = <0>;
 172                                 };
 173                                 pins2 {
 174                                         pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
 175                                         bias-disable;
 176                                 };
 177                         };
 178
 179                         fmc_pins: fmc@0 {
 180                                   pins {
 181                                           pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
 182                                                   <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
 183                                                   <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
 184                                                   <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
 185                                                   <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
 186                                                   <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
 187                                                   <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
 188
 189                                                   <STM32H7_PE0_FUNC_FMC_NBL0>,
 190                                                   <STM32H7_PE1_FUNC_FMC_NBL1>,
 191                                                   <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
 192                                                   <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
 193                                                   <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
 194                                                   <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
 195                                                   <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
 196                                                   <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
 197                                                   <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
 198                                                   <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
 199                                                   <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
 200
 201                                                   <STM32H7_PF0_FUNC_FMC_A0>,
 202                                                   <STM32H7_PF1_FUNC_FMC_A1>,
 203                                                   <STM32H7_PF2_FUNC_FMC_A2>,
 204                                                   <STM32H7_PF3_FUNC_FMC_A3>,
 205                                                   <STM32H7_PF4_FUNC_FMC_A4>,
 206                                                   <STM32H7_PF5_FUNC_FMC_A5>,
 207                                                   <STM32H7_PF11_FUNC_FMC_SDNRAS>,
 208                                                   <STM32H7_PF12_FUNC_FMC_A6>,
 209                                                   <STM32H7_PF13_FUNC_FMC_A7>,
 210                                                   <STM32H7_PF14_FUNC_FMC_A8>,
 211                                                   <STM32H7_PF15_FUNC_FMC_A9>,
 212
 213                                                   <STM32H7_PG0_FUNC_FMC_A10>,
 214                                                   <STM32H7_PG1_FUNC_FMC_A11>,
 215                                                   <STM32H7_PG2_FUNC_FMC_A12>,
 216                                                   <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
 217                                                   <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
 218                                                   <STM32H7_PG8_FUNC_FMC_SDCLK>,
 219                                                   <STM32H7_PG15_FUNC_FMC_SDNCAS>,
 220
 221                                                   <STM32H7_PH5_FUNC_FMC_SDNWE>,
 222                                                   <STM32H7_PH6_FUNC_FMC_SDNE1>,
 223                                                   <STM32H7_PH7_FUNC_FMC_SDCKE1>,
 224                                                   <STM32H7_PH8_FUNC_FMC_D16>,
 225                                                   <STM32H7_PH9_FUNC_FMC_D17>,
 226                                                   <STM32H7_PH10_FUNC_FMC_D18>,
 227                                                   <STM32H7_PH11_FUNC_FMC_D19>,
 228                                                   <STM32H7_PH12_FUNC_FMC_D20>,
 229                                                   <STM32H7_PH13_FUNC_FMC_D21>,
 230                                                   <STM32H7_PH14_FUNC_FMC_D22>,
 231                                                   <STM32H7_PH15_FUNC_FMC_D23>,
 232
 233                                                   <STM32H7_PI0_FUNC_FMC_D24>,
 234                                                   <STM32H7_PI1_FUNC_FMC_D25>,
 235                                                   <STM32H7_PI2_FUNC_FMC_D26>,
 236                                                   <STM32H7_PI3_FUNC_FMC_D27>,
 237                                                   <STM32H7_PI4_FUNC_FMC_NBL2>,
 238                                                   <STM32H7_PI5_FUNC_FMC_NBL3>,
 239                                                   <STM32H7_PI6_FUNC_FMC_D28>,
 240                                                   <STM32H7_PI7_FUNC_FMC_D29>,
 241                                                   <STM32H7_PI9_FUNC_FMC_D30>,
 242                                                   <STM32H7_PI10_FUNC_FMC_D31>;
 243
 244                                           slew-rate = <3>;
 245                                 };
 246                         };
 247
 248                         sdmmc1_pins: sdmmc@0 {
 249                                 pins {
 250                                         pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
 251                                                  <STM32H7_PC9_FUNC_SDMMC1_D1>,
 252                                                  <STM32H7_PC10_FUNC_SDMMC1_D2>,
 253                                                  <STM32H7_PC11_FUNC_SDMMC1_D3>,
 254                                                  <STM32H7_PC12_FUNC_SDMMC1_CK>,
 255                                                  <STM32H7_PD2_FUNC_SDMMC1_CMD>;
 256
 257                                         slew-rate = <3>;
 258                                         drive-push-pull;
 259                                         bias-disable;
 260                                 };
 261                         };
 262
 263                         pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
 264                                 pins {
 265                                         pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
 266                                                  <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
 267                                                  <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
 268                                                  <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
 269                                         drive-push-pull;
 270                                         slew-rate = <3>;
 271                                 };
 272                         };
 273                 };
 274         };
 275 };