1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/memory/stm32-sdram.h>
32 compatible = "st,stm32h7-fmc";
33 reg = <0x52004000 0x1000>;
34 clocks = <&rcc FMC_CK>;
36 pinctrl-0 = <&fmc_pins>;
37 pinctrl-names = "default";
41 * Memory configuration from sdram datasheet IS42S32800G-6BLI
42 * firsct bank is bank@0
43 * second bank is bank@1
46 st,sdram-control = /bits/ 8 <NO_COL_9
54 st,sdram-timing = /bits/ 8 <TMRD_1
61 st,sdram-refcount = <1539>;
65 sdmmc1: sdmmc@52007000 {
66 compatible = "st,stm32-sdmmc2";
67 reg = <0x52007000 0x1000>;
69 clocks = <&rcc SDMMC1_CK>;
70 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
97 compatible = "st,stm32-gpio";
102 compatible = "st,stm32-gpio";
107 compatible = "st,stm32-gpio";
112 compatible = "st,stm32-gpio";
117 compatible = "st,stm32-gpio";
122 compatible = "st,stm32-gpio";
127 compatible = "st,stm32-gpio";
132 compatible = "st,stm32-gpio";
137 compatible = "st,stm32-gpio";
142 compatible = "st,stm32-gpio";
147 compatible = "st,stm32-gpio";
153 pinmux = <STM32_PINMUX('D', 0, AF12)>,
154 <STM32_PINMUX('D', 1, AF12)>,
155 <STM32_PINMUX('D', 8, AF12)>,
156 <STM32_PINMUX('D', 9, AF12)>,
157 <STM32_PINMUX('D',10, AF12)>,
158 <STM32_PINMUX('D',14, AF12)>,
159 <STM32_PINMUX('D',15, AF12)>,
161 <STM32_PINMUX('E', 0, AF12)>,
162 <STM32_PINMUX('E', 1, AF12)>,
163 <STM32_PINMUX('E', 7, AF12)>,
164 <STM32_PINMUX('E', 8, AF12)>,
165 <STM32_PINMUX('E', 9, AF12)>,
166 <STM32_PINMUX('E',10, AF12)>,
167 <STM32_PINMUX('E',11, AF12)>,
168 <STM32_PINMUX('E',12, AF12)>,
169 <STM32_PINMUX('E',13, AF12)>,
170 <STM32_PINMUX('E',14, AF12)>,
171 <STM32_PINMUX('E',15, AF12)>,
173 <STM32_PINMUX('F', 0, AF12)>,
174 <STM32_PINMUX('F', 1, AF12)>,
175 <STM32_PINMUX('F', 2, AF12)>,
176 <STM32_PINMUX('F', 3, AF12)>,
177 <STM32_PINMUX('F', 4, AF12)>,
178 <STM32_PINMUX('F', 5, AF12)>,
179 <STM32_PINMUX('F',11, AF12)>,
180 <STM32_PINMUX('F',12, AF12)>,
181 <STM32_PINMUX('F',13, AF12)>,
182 <STM32_PINMUX('F',14, AF12)>,
183 <STM32_PINMUX('F',15, AF12)>,
185 <STM32_PINMUX('G', 0, AF12)>,
186 <STM32_PINMUX('G', 1, AF12)>,
187 <STM32_PINMUX('G', 2, AF12)>,
188 <STM32_PINMUX('G', 4, AF12)>,
189 <STM32_PINMUX('G', 5, AF12)>,
190 <STM32_PINMUX('G', 8, AF12)>,
191 <STM32_PINMUX('G',15, AF12)>,
193 <STM32_PINMUX('H', 5, AF12)>,
194 <STM32_PINMUX('H', 6, AF12)>,
195 <STM32_PINMUX('H', 7, AF12)>,
196 <STM32_PINMUX('H', 8, AF12)>,
197 <STM32_PINMUX('H', 9, AF12)>,
198 <STM32_PINMUX('H',10, AF12)>,
199 <STM32_PINMUX('H',11, AF12)>,
200 <STM32_PINMUX('H',12, AF12)>,
201 <STM32_PINMUX('H',13, AF12)>,
202 <STM32_PINMUX('H',14, AF12)>,
203 <STM32_PINMUX('H',15, AF12)>,
205 <STM32_PINMUX('I', 0, AF12)>,
206 <STM32_PINMUX('I', 1, AF12)>,
207 <STM32_PINMUX('I', 2, AF12)>,
208 <STM32_PINMUX('I', 3, AF12)>,
209 <STM32_PINMUX('I', 4, AF12)>,
210 <STM32_PINMUX('I', 5, AF12)>,
211 <STM32_PINMUX('I', 6, AF12)>,
212 <STM32_PINMUX('I', 7, AF12)>,
213 <STM32_PINMUX('I', 9, AF12)>,
214 <STM32_PINMUX('I',10, AF12)>;
220 pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
222 pinmux = <STM32_PINMUX('B', 8, AF7)>,
223 <STM32_PINMUX('B', 9, AF7)>,
224 <STM32_PINMUX('C', 6, AF8)>,
225 <STM32_PINMUX('C', 7, AF8)>;
231 sdmmc1_pins: sdmmc@0 {
233 pinmux = <STM32_PINMUX('C', 8, AF12)>,
234 <STM32_PINMUX('C', 9, AF12)>,
235 <STM32_PINMUX('C',10, AF12)>,
236 <STM32_PINMUX('C',11, AF12)>,
237 <STM32_PINMUX('C',12, AF12)>,
238 <STM32_PINMUX('D', 2, AF12)>;