arch/arm/dts/stm32h7-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <dt-bindings/memory/stm32-sdram.h>
   4
   5 /{
   6         clocks {
   7                 u-boot,dm-pre-reloc;
   8         };
   9
  10         aliases {
  11                 gpio0 = &gpioa;
  12                 gpio1 = &gpiob;
  13                 gpio2 = &gpioc;
  14                 gpio3 = &gpiod;
  15                 gpio4 = &gpioe;
  16                 gpio5 = &gpiof;
  17                 gpio6 = &gpiog;
  18                 gpio7 = &gpioh;
  19                 gpio8 = &gpioi;
  20                 gpio9 = &gpioj;
  21                 gpio10 = &gpiok;
  22                 mmc0 = &sdmmc1;
  23         };
  24
  25         soc {
  26                 u-boot,dm-pre-reloc;
  27                 pin-controller {
  28                         u-boot,dm-pre-reloc;
  29                 };
  30
  31                 fmc: fmc@52004000 {
  32                         compatible = "st,stm32h7-fmc";
  33                         reg = <0x52004000 0x1000>;
  34                         clocks = <&rcc FMC_CK>;
  35
  36                         pinctrl-0 = <&fmc_pins>;
  37                         pinctrl-names = "default";
  38                         status = "okay";
  39
  40                         /*
  41                          * Memory configuration from sdram datasheet IS42S32800G-6BLI
  42                          * firsct bank is bank@0
  43                          * second bank is bank@1
  44                          */
  45                         bank1: bank@1 {
  46                                 st,sdram-control = /bits/ 8 <NO_COL_9
  47                                                              NO_ROW_12
  48                                                              MWIDTH_32
  49                                                              BANKS_4
  50                                                              CAS_2
  51                                                              SDCLK_3
  52                                                              RD_BURST_EN
  53                                                              RD_PIPE_DL_0>;
  54                                 st,sdram-timing = /bits/ 8 <TMRD_1
  55                                                             TXSR_1
  56                                                             TRAS_1
  57                                                             TRC_6
  58                                                             TRP_2
  59                                                             TWR_1
  60                                                             TRCD_1>;
  61                                 st,sdram-refcount = <1539>;
  62                         };
  63                 };
  64
  65                 sdmmc1: sdmmc@52007000 {
  66                         compatible = "st,stm32-sdmmc2";
  67                         reg = <0x52007000 0x1000>;
  68                         interrupts = <49>;
  69                         clocks = <&rcc SDMMC1_CK>;
  70                         resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
  71                         st,idma = <1>;
  72                         cap-sd-highspeed;
  73                         cap-mmc-highspeed;
  74                 };
  75         };
  76 };
  77
  78 &clk_hse {
  79         u-boot,dm-pre-reloc;
  80 };
  81
  82 &clk_i2s {
  83         u-boot,dm-pre-reloc;
  84 };
  85
  86 &clk_lse {
  87         u-boot,dm-pre-reloc;
  88 };
  89
  90
  91 &fmc {
  92         u-boot,dm-pre-reloc;
  93 };
  94
  95 &gpioa {
  96         u-boot,dm-pre-reloc;
  97         compatible = "st,stm32-gpio";
  98 };
  99
 100 &gpiob {
 101         u-boot,dm-pre-reloc;
 102         compatible = "st,stm32-gpio";
 103 };
 104
 105 &gpioc {
 106         u-boot,dm-pre-reloc;
 107         compatible = "st,stm32-gpio";
 108 };
 109
 110 &gpiod {
 111         u-boot,dm-pre-reloc;
 112         compatible = "st,stm32-gpio";
 113 };
 114
 115 &gpioe {
 116         u-boot,dm-pre-reloc;
 117         compatible = "st,stm32-gpio";
 118 };
 119
 120 &gpiof {
 121         u-boot,dm-pre-reloc;
 122         compatible = "st,stm32-gpio";
 123 };
 124
 125 &gpiog {
 126         u-boot,dm-pre-reloc;
 127         compatible = "st,stm32-gpio";
 128 };
 129
 130 &gpioh {
 131         u-boot,dm-pre-reloc;
 132         compatible = "st,stm32-gpio";
 133 };
 134
 135 &gpioi {
 136         u-boot,dm-pre-reloc;
 137         compatible = "st,stm32-gpio";
 138 };
 139
 140 &gpioj {
 141         u-boot,dm-pre-reloc;
 142         compatible = "st,stm32-gpio";
 143 };
 144
 145 &gpiok {
 146         u-boot,dm-pre-reloc;
 147         compatible = "st,stm32-gpio";
 148 };
 149
 150 &pinctrl {
 151         fmc_pins: fmc@0 {
 152                 pins {
 153                         pinmux = <STM32_PINMUX('D', 0, AF12)>,
 154                                  <STM32_PINMUX('D', 1, AF12)>,
 155                                  <STM32_PINMUX('D', 8, AF12)>,
 156                                  <STM32_PINMUX('D', 9, AF12)>,
 157                                  <STM32_PINMUX('D',10, AF12)>,
 158                                  <STM32_PINMUX('D',14, AF12)>,
 159                                  <STM32_PINMUX('D',15, AF12)>,
 160
 161                                  <STM32_PINMUX('E', 0, AF12)>,
 162                                  <STM32_PINMUX('E', 1, AF12)>,
 163                                  <STM32_PINMUX('E', 7, AF12)>,
 164                                  <STM32_PINMUX('E', 8, AF12)>,
 165                                  <STM32_PINMUX('E', 9, AF12)>,
 166                                  <STM32_PINMUX('E',10, AF12)>,
 167                                  <STM32_PINMUX('E',11, AF12)>,
 168                                  <STM32_PINMUX('E',12, AF12)>,
 169                                  <STM32_PINMUX('E',13, AF12)>,
 170                                  <STM32_PINMUX('E',14, AF12)>,
 171                                  <STM32_PINMUX('E',15, AF12)>,
 172
 173                                  <STM32_PINMUX('F', 0, AF12)>,
 174                                  <STM32_PINMUX('F', 1, AF12)>,
 175                                  <STM32_PINMUX('F', 2, AF12)>,
 176                                  <STM32_PINMUX('F', 3, AF12)>,
 177                                  <STM32_PINMUX('F', 4, AF12)>,
 178                                  <STM32_PINMUX('F', 5, AF12)>,
 179                                  <STM32_PINMUX('F',11, AF12)>,
 180                                  <STM32_PINMUX('F',12, AF12)>,
 181                                  <STM32_PINMUX('F',13, AF12)>,
 182                                  <STM32_PINMUX('F',14, AF12)>,
 183                                  <STM32_PINMUX('F',15, AF12)>,
 184
 185                                  <STM32_PINMUX('G', 0, AF12)>,
 186                                  <STM32_PINMUX('G', 1, AF12)>,
 187                                  <STM32_PINMUX('G', 2, AF12)>,
 188                                  <STM32_PINMUX('G', 4, AF12)>,
 189                                  <STM32_PINMUX('G', 5, AF12)>,
 190                                  <STM32_PINMUX('G', 8, AF12)>,
 191                                  <STM32_PINMUX('G',15, AF12)>,
 192
 193                                  <STM32_PINMUX('H', 5, AF12)>,
 194                                  <STM32_PINMUX('H', 6, AF12)>,
 195                                  <STM32_PINMUX('H', 7, AF12)>,
 196                                  <STM32_PINMUX('H', 8, AF12)>,
 197                                  <STM32_PINMUX('H', 9, AF12)>,
 198                                  <STM32_PINMUX('H',10, AF12)>,
 199                                  <STM32_PINMUX('H',11, AF12)>,
 200                                  <STM32_PINMUX('H',12, AF12)>,
 201                                  <STM32_PINMUX('H',13, AF12)>,
 202                                  <STM32_PINMUX('H',14, AF12)>,
 203                                  <STM32_PINMUX('H',15, AF12)>,
 204
 205                                  <STM32_PINMUX('I', 0, AF12)>,
 206                                  <STM32_PINMUX('I', 1, AF12)>,
 207                                  <STM32_PINMUX('I', 2, AF12)>,
 208                                  <STM32_PINMUX('I', 3, AF12)>,
 209                                  <STM32_PINMUX('I', 4, AF12)>,
 210                                  <STM32_PINMUX('I', 5, AF12)>,
 211                                  <STM32_PINMUX('I', 6, AF12)>,
 212                                  <STM32_PINMUX('I', 7, AF12)>,
 213                                  <STM32_PINMUX('I', 9, AF12)>,
 214                                  <STM32_PINMUX('I',10, AF12)>;
 215
 216                         slew-rate = <3>;
 217                 };
 218         };
 219
 220         pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
 221                 pins {
 222                         pinmux = <STM32_PINMUX('B', 8, AF7)>,
 223                                  <STM32_PINMUX('B', 9, AF7)>,
 224                                  <STM32_PINMUX('C', 6, AF8)>,
 225                                  <STM32_PINMUX('C', 7, AF8)>;
 226                         drive-push-pull;
 227                         slew-rate = <3>;
 228                 };
 229         };
 230
 231         sdmmc1_pins: sdmmc@0 {
 232                 pins {
 233                         pinmux = <STM32_PINMUX('C', 8, AF12)>,
 234                                  <STM32_PINMUX('C', 9, AF12)>,
 235                                  <STM32_PINMUX('C',10, AF12)>,
 236                                  <STM32_PINMUX('C',11, AF12)>,
 237                                  <STM32_PINMUX('C',12, AF12)>,
 238                                  <STM32_PINMUX('D', 2, AF12)>;
 239
 240                         slew-rate = <3>;
 241                         drive-push-pull;
 242                         bias-disable;
 243                 };
 244         };
 245 };
 246
 247 &pwrcfg {
 248         u-boot,dm-pre-reloc;
 249 };
 250
 251 &rcc {
 252         u-boot,dm-pre-reloc;
 253 };