arm64: zynqmp: Use only earlycon bootargs instead of full one
[oweals/u-boot.git] / arch / arm / dts / stm32f769-disco.dts
1 /*
2  * Copyright 2016 - Vikas Manocha <vikas.manocha@st.com>
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 /dts-v1/;
44 #include "stm32f746.dtsi"
45 #include <dt-bindings/memory/stm32-sdram.h>
46
47 / {
48         model = "STMicroelectronics STM32F769-DISCO board";
49         compatible = "st,stm32f769-disco", "st,stm32f7";
50
51         chosen {
52                 bootargs = "root=/dev/ram rdinit=/linuxrc";
53                 stdout-path = "serial0:115200n8";
54         };
55
56         memory {
57                 reg = <0xC0000000 0x1000000>;
58         };
59
60         aliases {
61                 serial0 = &usart1;
62                 spi0 = &qspi;
63                 /* Aliases for gpios so as to use sequence */
64                 gpio0 = &gpioa;
65                 gpio1 = &gpiob;
66                 gpio2 = &gpioc;
67                 gpio3 = &gpiod;
68                 gpio4 = &gpioe;
69                 gpio5 = &gpiof;
70                 gpio6 = &gpiog;
71                 gpio7 = &gpioh;
72                 gpio8 = &gpioi;
73                 gpio9 = &gpioj;
74                 gpio10 = &gpiok;
75         };
76
77         led1 {
78                 compatible = "st,led1";
79                 led-gpio = <&gpioj 5 0>;
80         };
81
82         button1 {
83                 compatible = "st,button1";
84                 button-gpio = <&gpioa 0 0>;
85         };
86 };
87
88 &clk_hse {
89         clock-frequency = <25000000>;
90 };
91
92 &pinctrl {
93         usart1_pins_a: usart1@0 {
94                 pins1 {
95                        pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
96                                 bias-disable;
97                                 drive-push-pull;
98                                 slew-rate = <2>;
99                 };
100                 pins2 {
101                         pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
102                         bias-disable;
103                 };
104         };
105
106         ethernet_mii: mii@0 {
107               pins {
108                       pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
109                              <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
110                              <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
111                              <STM32F746_PA2_FUNC_ETH_MDIO>,
112                              <STM32F746_PC1_FUNC_ETH_MDC>,
113                              <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
114                              <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
115                              <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
116                              <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
117                       slew-rate = <2>;
118               };
119         };
120
121         qspi_pins: qspi@0 {
122                 pins {
123                         pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
124                                <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
125                                <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
126                                <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
127                                <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
128                                <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
129                         slew-rate = <2>;
130                 };
131         };
132
133         fmc_pins: fmc@0 {
134                   pins {
135                           pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
136                                  <STM32F746_PI9_FUNC_FMC_D30>,
137                                  <STM32F746_PI7_FUNC_FMC_D29>,
138                                  <STM32F746_PI6_FUNC_FMC_D28>,
139                                  <STM32F746_PI3_FUNC_FMC_D27>,
140                                  <STM32F746_PI2_FUNC_FMC_D26>,
141                                  <STM32F746_PI1_FUNC_FMC_D25>,
142                                  <STM32F746_PI0_FUNC_FMC_D24>,
143                                  <STM32F746_PH15_FUNC_FMC_D23>,
144                                  <STM32F746_PH14_FUNC_FMC_D22>,
145                                  <STM32F746_PH13_FUNC_FMC_D21>,
146                                  <STM32F746_PH12_FUNC_FMC_D20>,
147                                  <STM32F746_PH11_FUNC_FMC_D19>,
148                                  <STM32F746_PH10_FUNC_FMC_D18>,
149                                  <STM32F746_PH9_FUNC_FMC_D17>,
150                                  <STM32F746_PH8_FUNC_FMC_D16>,
151
152                                  <STM32F746_PD10_FUNC_FMC_D15>,
153                                  <STM32F746_PD9_FUNC_FMC_D14>,
154                                  <STM32F746_PD8_FUNC_FMC_D13>,
155                                  <STM32F746_PE15_FUNC_FMC_D12>,
156                                  <STM32F746_PE14_FUNC_FMC_D11>,
157                                  <STM32F746_PE13_FUNC_FMC_D10>,
158                                  <STM32F746_PE12_FUNC_FMC_D9>,
159                                  <STM32F746_PE11_FUNC_FMC_D8>,
160                                  <STM32F746_PE10_FUNC_FMC_D7>,
161                                  <STM32F746_PE9_FUNC_FMC_D6>,
162                                  <STM32F746_PE8_FUNC_FMC_D5>,
163                                  <STM32F746_PE7_FUNC_FMC_D4>,
164                                  <STM32F746_PD1_FUNC_FMC_D3>,
165                                  <STM32F746_PD0_FUNC_FMC_D2>,
166                                  <STM32F746_PD15_FUNC_FMC_D1>,
167                                  <STM32F746_PD14_FUNC_FMC_D0>,
168
169                                  <STM32F746_PI5_FUNC_FMC_NBL3>,
170                                  <STM32F746_PI4_FUNC_FMC_NBL2>,
171                                  <STM32F746_PE1_FUNC_FMC_NBL1>,
172                                  <STM32F746_PE0_FUNC_FMC_NBL0>,
173
174                                  <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
175                                  <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
176
177                                  <STM32F746_PG1_FUNC_FMC_A11>,
178                                  <STM32F746_PG0_FUNC_FMC_A10>,
179                                  <STM32F746_PF15_FUNC_FMC_A9>,
180                                  <STM32F746_PF14_FUNC_FMC_A8>,
181                                  <STM32F746_PF13_FUNC_FMC_A7>,
182                                  <STM32F746_PF12_FUNC_FMC_A6>,
183                                  <STM32F746_PF5_FUNC_FMC_A5>,
184                                  <STM32F746_PF4_FUNC_FMC_A4>,
185                                  <STM32F746_PF3_FUNC_FMC_A3>,
186                                  <STM32F746_PF2_FUNC_FMC_A2>,
187                                  <STM32F746_PF1_FUNC_FMC_A1>,
188                                  <STM32F746_PF0_FUNC_FMC_A0>,
189
190                                  <STM32F746_PH3_FUNC_FMC_SDNE0>,
191                                  <STM32F746_PH5_FUNC_FMC_SDNWE>,
192                                  <STM32F746_PF11_FUNC_FMC_SDNRAS>,
193                                  <STM32F746_PG15_FUNC_FMC_SDNCAS>,
194                                  <STM32F746_PH2_FUNC_FMC_SDCKE0>,
195                                  <STM32F746_PG8_FUNC_FMC_SDCLK>;
196                           slew-rate = <2>;
197                   };
198           };
199 };
200
201 &usart1 {
202         pinctrl-0 = <&usart1_pins_a>;
203         pinctrl-names = "default";
204         status = "okay";
205 };
206
207 &fmc {
208         pinctrl-0 = <&fmc_pins>;
209         pinctrl-names = "default";
210         status = "okay";
211
212         /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
213         bank1: bank@0 {
214                st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_32 BANKS_4
215                                             CAS_3 SDCLK_2 RD_BURST_EN
216                                             RD_PIPE_DL_0>;
217                st,sdram-timing = /bits/ 8 <TMRD_2 TXSR_6 TRAS_4 TRC_6 TWR_2
218                                            TRP_2 TRCD_2>;
219                 /* refcount = (64msec/total_row_sdram)*freq - 20 */
220                st,sdram-refcount = < 1542 >;
221        };
222 };
223
224 &mac {
225         status = "okay";
226         pinctrl-0 = <&ethernet_mii>;
227         phy-mode = "rmii";
228         phy-handle = <&phy0>;
229
230         mdio0 {
231                 #address-cells = <1>;
232                 #size-cells = <0>;
233                 compatible = "snps,dwmac-mdio";
234                 phy0: ethernet-phy@0 {
235                         reg = <0>;
236                 };
237         };
238 };
239
240 &qspi {
241         pinctrl-0 = <&qspi_pins>;
242         status = "okay";
243
244         qflash0: n25q128a {
245                         #address-cells = <1>;
246                         #size-cells = <1>;
247                         compatible = "micron,n25q128a13", "spi-flash";
248                         spi-max-frequency = <108000000>;
249                         spi-tx-bus-width = <1>;
250                         spi-rx-bus-width = <1>;
251                         memory-map = <0x90000000 0x1000000>;
252                         reg = <0>;
253         };
254 };