arch/arm/dts/stm32f769-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <stm32f7-u-boot.dtsi>
   4 /{
   5         chosen {
   6                 bootargs = "root=/dev/ram rdinit=/linuxrc";
   7         };
   8
   9         aliases {
  10                 /* Aliases for gpios so as to use sequence */
  11                 gpio0 = &gpioa;
  12                 gpio1 = &gpiob;
  13                 gpio2 = &gpioc;
  14                 gpio3 = &gpiod;
  15                 gpio4 = &gpioe;
  16                 gpio5 = &gpiof;
  17                 gpio6 = &gpiog;
  18                 gpio7 = &gpioh;
  19                 gpio8 = &gpioi;
  20                 gpio9 = &gpioj;
  21                 gpio10 = &gpiok;
  22                 mmc0 = &sdio2;
  23                 spi0 = &qspi;
  24         };
  25
  26         button1 {
  27                 compatible = "st,button1";
  28                 button-gpio = <&gpioa 0 0>;
  29         };
  30
  31         led1 {
  32                 compatible = "st,led1";
  33                 led-gpio = <&gpioj 5 0>;
  34         };
  35 };
  36
  37 &fmc {
  38         /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
  39         bank1: bank@0 {
  40                 u-boot,dm-pre-reloc;
  41                 st,sdram-control = /bits/ 8 <NO_COL_8
  42                                              NO_ROW_12
  43                                              MWIDTH_32
  44                                              BANKS_4
  45                                              CAS_3
  46                                              SDCLK_2
  47                                              RD_BURST_EN
  48                                              RD_PIPE_DL_0>;
  49                 st,sdram-timing = /bits/ 8 <TMRD_2
  50                                             TXSR_6
  51                                             TRAS_4
  52                                             TRC_6
  53                                             TWR_2
  54                                             TRP_2
  55                                             TRCD_2>;
  56                 /* refcount = (64msec/total_row_sdram)*freq - 20 */
  57                 st,sdram-refcount = < 1542 >;
  58         };
  59 };
  60
  61 &pinctrl {
  62         ethernet_mii: mii@0 {
  63                 pins {
  64                         pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
  65                                  <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
  66                                  <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
  67                                  <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
  68                                  <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
  69                                  <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
  70                                  <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
  71                                  <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
  72                                  <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
  73                         slew-rate = <2>;
  74                 };
  75         };
  76
  77         fmc_pins: fmc@0 {
  78                 pins {
  79                         pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
  80                                  <STM32_PINMUX('I', 9, AF12)>, /* D30 */
  81                                  <STM32_PINMUX('I', 7, AF12)>, /* D29 */
  82                                  <STM32_PINMUX('I', 6, AF12)>, /* D28 */
  83                                  <STM32_PINMUX('I', 3, AF12)>, /* D27 */
  84                                  <STM32_PINMUX('I', 2, AF12)>, /* D26 */
  85                                  <STM32_PINMUX('I', 1, AF12)>, /* D25 */
  86                                  <STM32_PINMUX('I', 0, AF12)>, /* D24 */
  87                                  <STM32_PINMUX('H',15, AF12)>, /* D23 */
  88                                  <STM32_PINMUX('H',14, AF12)>, /* D22 */
  89                                  <STM32_PINMUX('H',13, AF12)>, /* D21 */
  90                                  <STM32_PINMUX('H',12, AF12)>, /* D20 */
  91                                  <STM32_PINMUX('H',11, AF12)>, /* D19 */
  92                                  <STM32_PINMUX('H',10, AF12)>, /* D18 */
  93                                  <STM32_PINMUX('H', 9, AF12)>, /* D17 */
  94                                  <STM32_PINMUX('H', 8, AF12)>, /* D16 */
  95
  96                                  <STM32_PINMUX('D',10, AF12)>, /* D15 */
  97                                  <STM32_PINMUX('D', 9, AF12)>, /* D14 */
  98                                  <STM32_PINMUX('D', 8, AF12)>, /* D13 */
  99                                  <STM32_PINMUX('E',15, AF12)>, /* D12 */
 100                                  <STM32_PINMUX('E',14, AF12)>, /* D11 */
 101                                  <STM32_PINMUX('E',13, AF12)>, /* D10 */
 102                                  <STM32_PINMUX('E',12, AF12)>, /* D9 */
 103                                  <STM32_PINMUX('E',11, AF12)>, /* D8 */
 104                                  <STM32_PINMUX('E',10, AF12)>, /* D7 */
 105                                  <STM32_PINMUX('E', 9, AF12)>, /* D6 */
 106                                  <STM32_PINMUX('E', 8, AF12)>, /* D5 */
 107                                  <STM32_PINMUX('E', 7, AF12)>, /* D4 */
 108                                  <STM32_PINMUX('D', 1, AF12)>, /* D3 */
 109                                  <STM32_PINMUX('D', 0, AF12)>, /* D2 */
 110                                  <STM32_PINMUX('D',15, AF12)>, /* D1 */
 111                                  <STM32_PINMUX('D',14, AF12)>, /* D0 */
 112
 113                                  <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
 114                                  <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
 115                                  <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
 116                                  <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
 117
 118                                  <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
 119                                  <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
 120
 121                                  <STM32_PINMUX('G', 1, AF12)>, /* A11 */
 122                                  <STM32_PINMUX('G', 0, AF12)>, /* A10 */
 123                                  <STM32_PINMUX('F',15, AF12)>, /* A9 */
 124                                  <STM32_PINMUX('F',14, AF12)>, /* A8 */
 125                                  <STM32_PINMUX('F',13, AF12)>, /* A7 */
 126                                  <STM32_PINMUX('F',12, AF12)>, /* A6 */
 127                                  <STM32_PINMUX('F', 5, AF12)>, /* A5 */
 128                                  <STM32_PINMUX('F', 4, AF12)>, /* A4 */
 129                                  <STM32_PINMUX('F', 3, AF12)>, /* A3 */
 130                                  <STM32_PINMUX('F', 2, AF12)>, /* A2 */
 131                                  <STM32_PINMUX('F', 1, AF12)>, /* A1 */
 132                                  <STM32_PINMUX('F', 0, AF12)>, /* A0 */
 133
 134                                  <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
 135                                  <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
 136                                  <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
 137                                  <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
 138                                  <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
 139                                  <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
 140                         slew-rate = <2>;
 141                 };
 142         };
 143
 144         qspi_pins: qspi@0 {
 145                 pins {
 146                         pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
 147                                  <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
 148                                  <STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
 149                                  <STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
 150                                  <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
 151                                  <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
 152                         slew-rate = <2>;
 153                 };
 154         };
 155 };
 156
 157 &qspi {
 158         reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
 159         flash0: mx66l51235l {
 160                 #address-cells = <1>;
 161                 #size-cells = <1>;
 162                 compatible = "jedec,spi-nor";
 163                 spi-max-frequency = <108000000>;
 164                 spi-tx-bus-width = <4>;
 165                 spi-rx-bus-width = <4>;
 166                 reg = <0>;
 167         };
 168 };