arch/arm/dts/stm32f769-disco-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <stm32f7-u-boot.dtsi>
   4 /{
   5         chosen {
   6                 bootargs = "root=/dev/ram rdinit=/linuxrc";
   7         };
   8
   9         aliases {
  10                 /* Aliases for gpios so as to use sequence */
  11                 gpio0 = &gpioa;
  12                 gpio1 = &gpiob;
  13                 gpio2 = &gpioc;
  14                 gpio3 = &gpiod;
  15                 gpio4 = &gpioe;
  16                 gpio5 = &gpiof;
  17                 gpio6 = &gpiog;
  18                 gpio7 = &gpioh;
  19                 gpio8 = &gpioi;
  20                 gpio9 = &gpioj;
  21                 gpio10 = &gpiok;
  22                 mmc0 = &sdio2;
  23                 spi0 = &qspi;
  24         };
  25
  26         button1 {
  27                 compatible = "st,button1";
  28                 button-gpio = <&gpioa 0 0>;
  29         };
  30
  31         led1 {
  32                 compatible = "st,led1";
  33                 led-gpio = <&gpioj 5 0>;
  34         };
  35 };
  36
  37 &fmc {
  38         /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
  39         bank1: bank@0 {
  40                 u-boot,dm-pre-reloc;
  41                 st,sdram-control = /bits/ 8 <NO_COL_8
  42                                              NO_ROW_12
  43                                              MWIDTH_32
  44                                              BANKS_4
  45                                              CAS_3
  46                                              SDCLK_2
  47                                              RD_BURST_EN
  48                                              RD_PIPE_DL_0>;
  49                 st,sdram-timing = /bits/ 8 <TMRD_2
  50                                             TXSR_6
  51                                             TRAS_4
  52                                             TRC_6
  53                                             TWR_2
  54                                             TRP_2
  55                                             TRCD_2>;
  56                 /* refcount = (64msec/total_row_sdram)*freq - 20 */
  57                 st,sdram-refcount = < 1542 >;
  58         };
  59 };
  60
  61 &pinctrl {
  62         ethernet_mii: mii@0 {
  63                 pins {
  64                         pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
  65                                  <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
  66                                  <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
  67                                  <STM32F746_PA2_FUNC_ETH_MDIO>,
  68                                  <STM32F746_PC1_FUNC_ETH_MDC>,
  69                                  <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
  70                                  <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
  71                                  <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
  72                                  <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
  73                         slew-rate = <2>;
  74                 };
  75         };
  76
  77         fmc_pins: fmc@0 {
  78                 pins {
  79                         pinmux = <STM32F746_PI10_FUNC_FMC_D31>,
  80                                  <STM32F746_PI9_FUNC_FMC_D30>,
  81                                  <STM32F746_PI7_FUNC_FMC_D29>,
  82                                  <STM32F746_PI6_FUNC_FMC_D28>,
  83                                  <STM32F746_PI3_FUNC_FMC_D27>,
  84                                  <STM32F746_PI2_FUNC_FMC_D26>,
  85                                  <STM32F746_PI1_FUNC_FMC_D25>,
  86                                  <STM32F746_PI0_FUNC_FMC_D24>,
  87                                  <STM32F746_PH15_FUNC_FMC_D23>,
  88                                  <STM32F746_PH14_FUNC_FMC_D22>,
  89                                  <STM32F746_PH13_FUNC_FMC_D21>,
  90                                  <STM32F746_PH12_FUNC_FMC_D20>,
  91                                  <STM32F746_PH11_FUNC_FMC_D19>,
  92                                  <STM32F746_PH10_FUNC_FMC_D18>,
  93                                  <STM32F746_PH9_FUNC_FMC_D17>,
  94                                  <STM32F746_PH8_FUNC_FMC_D16>,
  95
  96                                  <STM32F746_PD10_FUNC_FMC_D15>,
  97                                  <STM32F746_PD9_FUNC_FMC_D14>,
  98                                  <STM32F746_PD8_FUNC_FMC_D13>,
  99                                  <STM32F746_PE15_FUNC_FMC_D12>,
 100                                  <STM32F746_PE14_FUNC_FMC_D11>,
 101                                  <STM32F746_PE13_FUNC_FMC_D10>,
 102                                  <STM32F746_PE12_FUNC_FMC_D9>,
 103                                  <STM32F746_PE11_FUNC_FMC_D8>,
 104                                  <STM32F746_PE10_FUNC_FMC_D7>,
 105                                  <STM32F746_PE9_FUNC_FMC_D6>,
 106                                  <STM32F746_PE8_FUNC_FMC_D5>,
 107                                  <STM32F746_PE7_FUNC_FMC_D4>,
 108                                  <STM32F746_PD1_FUNC_FMC_D3>,
 109                                  <STM32F746_PD0_FUNC_FMC_D2>,
 110                                  <STM32F746_PD15_FUNC_FMC_D1>,
 111                                  <STM32F746_PD14_FUNC_FMC_D0>,
 112
 113                                  <STM32F746_PI5_FUNC_FMC_NBL3>,
 114                                  <STM32F746_PI4_FUNC_FMC_NBL2>,
 115                                  <STM32F746_PE1_FUNC_FMC_NBL1>,
 116                                  <STM32F746_PE0_FUNC_FMC_NBL0>,
 117
 118                                  <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>,
 119                                  <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>,
 120
 121                                  <STM32F746_PG1_FUNC_FMC_A11>,
 122                                  <STM32F746_PG0_FUNC_FMC_A10>,
 123                                  <STM32F746_PF15_FUNC_FMC_A9>,
 124                                  <STM32F746_PF14_FUNC_FMC_A8>,
 125                                  <STM32F746_PF13_FUNC_FMC_A7>,
 126                                  <STM32F746_PF12_FUNC_FMC_A6>,
 127                                  <STM32F746_PF5_FUNC_FMC_A5>,
 128                                  <STM32F746_PF4_FUNC_FMC_A4>,
 129                                  <STM32F746_PF3_FUNC_FMC_A3>,
 130                                  <STM32F746_PF2_FUNC_FMC_A2>,
 131                                  <STM32F746_PF1_FUNC_FMC_A1>,
 132                                  <STM32F746_PF0_FUNC_FMC_A0>,
 133
 134                                  <STM32F746_PH3_FUNC_FMC_SDNE0>,
 135                                  <STM32F746_PH5_FUNC_FMC_SDNWE>,
 136                                  <STM32F746_PF11_FUNC_FMC_SDNRAS>,
 137                                  <STM32F746_PG15_FUNC_FMC_SDNCAS>,
 138                                  <STM32F746_PH2_FUNC_FMC_SDCKE0>,
 139                                  <STM32F746_PG8_FUNC_FMC_SDCLK>;
 140                         slew-rate = <2>;
 141                 };
 142         };
 143
 144         qspi_pins: qspi@0 {
 145                 pins {
 146                         pinmux = <STM32F746_PB2_FUNC_QUADSPI_CLK>,
 147                                  <STM32F746_PB6_FUNC_QUADSPI_BK1_NCS>,
 148                                  <STM32F746_PC9_FUNC_QUADSPI_BK1_IO0>,
 149                                  <STM32F746_PC10_FUNC_QUADSPI_BK1_IO1>,
 150                                  <STM32F746_PD13_FUNC_QUADSPI_BK1_IO3>,
 151                                  <STM32F746_PE2_FUNC_QUADSPI_BK1_IO2>;
 152                         slew-rate = <2>;
 153                 };
 154         };
 155 };
 156
 157 &qspi {
 158         flash0: mx66l51235l {
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 spi-max-frequency = <108000000>;
 162                 spi-rx-bus-width = <4>;
 163                 reg = <0>;
 164         };
 165 };