1 // SPDX-License-Identifier: GPL-2.0+
3 #include <stm32f7-u-boot.dtsi>
6 bootargs = "root=/dev/ram rdinit=/linuxrc";
10 /* Aliases for gpios so as to use sequence */
27 compatible = "st,button1";
28 button-gpio = <&gpioa 0 0>;
32 compatible = "synopsys,dw-mipi-dsi";
37 compatible = "st,led1";
38 led-gpio = <&gpioj 5 0>;
42 compatible = "orisetech,otm8009a";
43 reset-gpios = <&gpioj 15 1>;
48 remote-endpoint = <&dsi_out>;
55 compatible = "st,stm32-dsi";
56 reg = <0x40016C00 0x800>;
57 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
58 clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
59 <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
61 clock-names = "pclk", "px_clk", "ref";
68 remote-endpoint = <&panel_in>;
73 remote-endpoint = <&dp_out>;
79 ltdc: display-controller@40016800 {
80 compatible = "st,stm32-ltdc";
81 reg = <0x40016800 0x200>;
82 resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
83 clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
91 remote-endpoint = <&dsi_in>;
100 /* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
103 st,sdram-control = /bits/ 8 <NO_COL_8
111 st,sdram-timing = /bits/ 8 <TMRD_2
118 /* refcount = (64msec/total_row_sdram)*freq - 20 */
119 st,sdram-refcount = < 1542 >;
124 ethernet_mii: mii@0 {
126 pinmux = <STM32_PINMUX('G',13, AF11)>, /* ETH_RMII_TXD0 */
127 <STM32_PINMUX('G',14, AF11)>, /* ETH_RMII_TXD1 */
128 <STM32_PINMUX('G',11, AF11)>, /* ETH_RMII_TX_EN */
129 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
130 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
131 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */
132 <STM32_PINMUX('A', 7, AF11)>, /* ETH_RMII_CRS_DV */
133 <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */
134 <STM32_PINMUX('C', 5, AF11)>; /* ETH_RMII_RXD1 */
141 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
142 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
143 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
144 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
145 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
146 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
147 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
148 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
149 <STM32_PINMUX('H',15, AF12)>, /* D23 */
150 <STM32_PINMUX('H',14, AF12)>, /* D22 */
151 <STM32_PINMUX('H',13, AF12)>, /* D21 */
152 <STM32_PINMUX('H',12, AF12)>, /* D20 */
153 <STM32_PINMUX('H',11, AF12)>, /* D19 */
154 <STM32_PINMUX('H',10, AF12)>, /* D18 */
155 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
156 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
158 <STM32_PINMUX('D',10, AF12)>, /* D15 */
159 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
160 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
161 <STM32_PINMUX('E',15, AF12)>, /* D12 */
162 <STM32_PINMUX('E',14, AF12)>, /* D11 */
163 <STM32_PINMUX('E',13, AF12)>, /* D10 */
164 <STM32_PINMUX('E',12, AF12)>, /* D9 */
165 <STM32_PINMUX('E',11, AF12)>, /* D8 */
166 <STM32_PINMUX('E',10, AF12)>, /* D7 */
167 <STM32_PINMUX('E', 9, AF12)>, /* D6 */
168 <STM32_PINMUX('E', 8, AF12)>, /* D5 */
169 <STM32_PINMUX('E', 7, AF12)>, /* D4 */
170 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
171 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
172 <STM32_PINMUX('D',15, AF12)>, /* D1 */
173 <STM32_PINMUX('D',14, AF12)>, /* D0 */
175 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
176 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
177 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
178 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
180 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
181 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
183 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
184 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
185 <STM32_PINMUX('F',15, AF12)>, /* A9 */
186 <STM32_PINMUX('F',14, AF12)>, /* A8 */
187 <STM32_PINMUX('F',13, AF12)>, /* A7 */
188 <STM32_PINMUX('F',12, AF12)>, /* A6 */
189 <STM32_PINMUX('F', 5, AF12)>, /* A5 */
190 <STM32_PINMUX('F', 4, AF12)>, /* A4 */
191 <STM32_PINMUX('F', 3, AF12)>, /* A3 */
192 <STM32_PINMUX('F', 2, AF12)>, /* A2 */
193 <STM32_PINMUX('F', 1, AF12)>, /* A1 */
194 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
196 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
197 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
198 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
199 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
200 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
201 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
208 pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */
209 <STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
210 <STM32_PINMUX('C', 9, AF9)>, /* BK1_IO0 */
211 <STM32_PINMUX('C',10, AF9)>, /* BK1_IO1 */
212 <STM32_PINMUX('D',13, AF9)>, /* BK1_IO3 */
213 <STM32_PINMUX('E', 2, AF9)>; /* BK1_IO2 */
218 usart1_pins_a: usart1@0 {
230 reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
231 flash0: mx66l51235l {
232 #address-cells = <1>;
234 compatible = "jedec,spi-nor";
235 spi-max-frequency = <108000000>;
236 spi-tx-bus-width = <4>;
237 spi-rx-bus-width = <4>;