arch/arm/dts/stm32f746.dtsi

   1 /*
   2  * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>
   3  * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>
   4  *
   5  * Based on:
   6  * stm32f429.dtsi from Linux
   7  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPL or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This file is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of the
  17  *     License, or (at your option) any later version.
  18  *
  19  *     This file is distributed in the hope that it will be useful,
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "armv7-m.dtsi"
  49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>
  50 #include <dt-bindings/clock/stm32fx-clock.h>
  51 #include <dt-bindings/mfd/stm32f7-rcc.h>
  52
  53 / {
  54         clocks {
  55                 clk_hse: clk-hse {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <0>;
  59                 };
  60         };
  61
  62         soc {
  63                 usart1: serial@40011000 {
  64                         compatible = "st,stm32f7-usart", "st,stm32f7-uart";
  65                         reg = <0x40011000 0x400>;
  66                         interrupts = <37>;
  67                         clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
  68                         status = "disabled";
  69                 };
  70
  71                 pwrcfg: power-config@58024800 {
  72                         compatible = "syscon";
  73                         reg = <0x40007000 0x400>;
  74                 };
  75
  76                 rcc: rcc@40023810 {
  77                         #reset-cells = <1>;
  78                         #clock-cells = <2>;
  79                         compatible = "st,stm32f746-rcc", "st,stm32-rcc";
  80                         reg = <0x40023800 0x400>;
  81                         clocks = <&clk_hse>;
  82                         st,syscfg = <&pwrcfg>;
  83                 };
  84
  85                 pinctrl: pin-controller {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         compatible = "st,stm32f746-pinctrl";
  89                         ranges = <0 0x40020000 0x3000>;
  90                         pins-are-numbered;
  91
  92                         gpioa: gpio@40020000 {
  93                                 gpio-controller;
  94                                 #gpio-cells = <2>;
  95                                 compatible = "st,stm32-gpio";
  96                                 reg = <0x0 0x400>;
  97                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
  98                                 st,bank-name = "GPIOA";
  99                         };
 100
 101                         gpiob: gpio@40020400 {
 102                                 gpio-controller;
 103                                 #gpio-cells = <2>;
 104                                 compatible = "st,stm32-gpio";
 105                                 reg = <0x400 0x400>;
 106                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
 107                                 st,bank-name = "GPIOB";
 108                         };
 109
 110
 111                         gpioc: gpio@40020800 {
 112                                 gpio-controller;
 113                                 #gpio-cells = <2>;
 114                                 compatible = "st,stm32-gpio";
 115                                 reg = <0x800 0x400>;
 116                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
 117                                 st,bank-name = "GPIOC";
 118                         };
 119
 120                         gpiod: gpio@40020c00 {
 121                                 gpio-controller;
 122                                 #gpio-cells = <2>;
 123                                 compatible = "st,stm32-gpio";
 124                                 reg = <0xc00 0x400>;
 125                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
 126                                 st,bank-name = "GPIOD";
 127                         };
 128
 129                         gpioe: gpio@40021000 {
 130                                 gpio-controller;
 131                                 #gpio-cells = <2>;
 132                                 compatible = "st,stm32-gpio";
 133                                 reg = <0x1000 0x400>;
 134                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
 135                                 st,bank-name = "GPIOE";
 136                         };
 137
 138                         gpiof: gpio@40021400 {
 139                                 gpio-controller;
 140                                 #gpio-cells = <2>;
 141                                 compatible = "st,stm32-gpio";
 142                                 reg = <0x1400 0x400>;
 143                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
 144                                 st,bank-name = "GPIOF";
 145                         };
 146
 147                         gpiog: gpio@40021800 {
 148                                 gpio-controller;
 149                                 #gpio-cells = <2>;
 150                                 compatible = "st,stm32-gpio";
 151                                 reg = <0x1800 0x400>;
 152                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
 153                                 st,bank-name = "GPIOG";
 154                         };
 155
 156                         gpioh: gpio@40021c00 {
 157                                 gpio-controller;
 158                                 #gpio-cells = <2>;
 159                                 compatible = "st,stm32-gpio";
 160                                 reg = <0x1c00 0x400>;
 161                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
 162                                 st,bank-name = "GPIOH";
 163                         };
 164
 165                         gpioi: gpio@40022000 {
 166                                 gpio-controller;
 167                                 #gpio-cells = <2>;
 168                                 compatible = "st,stm32-gpio";
 169                                 reg = <0x2000 0x400>;
 170                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
 171                                 st,bank-name = "GPIOI";
 172                         };
 173
 174                         gpioj: gpio@40022400 {
 175                                 gpio-controller;
 176                                 #gpio-cells = <2>;
 177                                 compatible = "st,stm32-gpio";
 178                                 reg = <0x2400 0x400>;
 179                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
 180                                 st,bank-name = "GPIOJ";
 181                         };
 182
 183                         gpiok: gpio@40022800 {
 184                                 gpio-controller;
 185                                 #gpio-cells = <2>;
 186                                 compatible = "st,stm32-gpio";
 187                                 reg = <0x2800 0x400>;
 188                                 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
 189                                 st,bank-name = "GPIOK";
 190                         };
 191
 192                         sdio_pins: sdio_pins@0 {
 193                                 pins {
 194                                         pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
 195                                                  <STM32F746_PC9_FUNC_SDMMC1_D1>,
 196                                                  <STM32F746_PC10_FUNC_SDMMC1_D2>,
 197                                                  <STM32F746_PC11_FUNC_SDMMC1_D3>,
 198                                                  <STM32F746_PC12_FUNC_SDMMC1_CK>,
 199                                                  <STM32F746_PD2_FUNC_SDMMC1_CMD>;
 200                                         drive-push-pull;
 201                                         slew-rate = <2>;
 202                                 };
 203                         };
 204
 205                         sdio_pins_od: sdio_pins_od@0 {
 206                                 pins1 {
 207                                         pinmux = <STM32F746_PC8_FUNC_SDMMC1_D0>,
 208                                                  <STM32F746_PC9_FUNC_SDMMC1_D1>,
 209                                                  <STM32F746_PC10_FUNC_SDMMC1_D2>,
 210                                                  <STM32F746_PC11_FUNC_SDMMC1_D3>,
 211                                                  <STM32F746_PC12_FUNC_SDMMC1_CK>;
 212                                         drive-push-pull;
 213                                         slew-rate = <2>;
 214                                 };
 215
 216                                 pins2 {
 217                                         pinmux = <STM32F746_PD2_FUNC_SDMMC1_CMD>;
 218                                         drive-open-drain;
 219                                         slew-rate = <2>;
 220                                 };
 221                         };
 222
 223                         sdio_pins_b: sdio_pins_b@0 {
 224                                 pins {
 225                                         pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
 226                                                  <STM32F769_PG10_FUNC_SDMMC2_D1>,
 227                                                  <STM32F769_PB3_FUNC_SDMMC2_D2>,
 228                                                  <STM32F769_PB4_FUNC_SDMMC2_D3>,
 229                                                  <STM32F769_PD6_FUNC_SDMMC2_CLK>,
 230                                                  <STM32F769_PD7_FUNC_SDMMC2_CMD>;
 231                                         drive-push-pull;
 232                                         slew-rate = <2>;
 233                                 };
 234                         };
 235
 236                         sdio_pins_od_b: sdio_pins_od_b@0 {
 237                                 pins1 {
 238                                         pinmux = <STM32F769_PG9_FUNC_SDMMC2_D0>,
 239                                                  <STM32F769_PG10_FUNC_SDMMC2_D1>,
 240                                                  <STM32F769_PB3_FUNC_SDMMC2_D2>,
 241                                                  <STM32F769_PB4_FUNC_SDMMC2_D3>,
 242                                                  <STM32F769_PD6_FUNC_SDMMC2_CLK>;
 243                                         drive-push-pull;
 244                                         slew-rate = <2>;
 245                                 };
 246
 247                                 pins2 {
 248                                         pinmux = <STM32F769_PD7_FUNC_SDMMC2_CMD>;
 249                                         drive-open-drain;
 250                                         slew-rate = <2>;
 251                                 };
 252                         };
 253
 254                 };
 255                 sdio: sdio@40012c00 {
 256                         compatible = "st,stm32f4xx-sdio";
 257                         reg = <0x40012c00 0x400>;
 258                         clocks = <&rcc 0 171>;
 259                         interrupts = <49>;
 260                         status = "disabled";
 261                         pinctrl-0 = <&sdio_pins>;
 262                         pinctrl-1 = <&sdio_pins_od>;
 263                         pinctrl-names = "default", "opendrain";
 264                         max-frequency = <48000000>;
 265                 };
 266
 267                 sdio2: sdio2@40011c00 {
 268                         compatible = "st,stm32f4xx-sdio";
 269                         reg = <0x40011c00 0x400>;
 270                         clocks = <&rcc 0 167>;
 271                         interrupts = <103>;
 272                         status = "disabled";
 273                         pinctrl-0 = <&sdio_pins_b>;
 274                         pinctrl-1 = <&sdio_pins_od_b>;
 275                         pinctrl-names = "default", "opendrain";
 276                         max-frequency = <48000000>;
 277                 };
 278
 279                 timer5: timer@40000c00 {
 280                         compatible = "st,stm32-timer";
 281                         reg = <0x40000c00 0x400>;
 282                         interrupts = <50>;
 283                         clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 284                 };
 285         };
 286 };
 287
 288 &systick {
 289         status = "okay";
 290 };