2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/clock/stm32fx-clock.h>
46 #include <dt-bindings/mfd/stm32f7-rcc.h>
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
64 compatible = "fixed-clock";
65 clock-frequency = <32000>;
68 clk_i2s_ckin: clk-i2s-ckin {
70 compatible = "fixed-clock";
71 clock-frequency = <48000000>;
76 timer2: timer@40000000 {
77 compatible = "st,stm32-timer";
78 reg = <0x40000000 0x400>;
80 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
84 timers2: timers@40000000 {
87 compatible = "st,stm32-timers";
88 reg = <0x40000000 0x400>;
89 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
94 compatible = "st,stm32-pwm";
99 compatible = "st,stm32-timer-trigger";
105 timer3: timer@40000400 {
106 compatible = "st,stm32-timer";
107 reg = <0x40000400 0x400>;
109 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
113 timers3: timers@40000400 {
114 #address-cells = <1>;
116 compatible = "st,stm32-timers";
117 reg = <0x40000400 0x400>;
118 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
123 compatible = "st,stm32-pwm";
128 compatible = "st,stm32-timer-trigger";
134 timer4: timer@40000800 {
135 compatible = "st,stm32-timer";
136 reg = <0x40000800 0x400>;
138 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
142 timers4: timers@40000800 {
143 #address-cells = <1>;
145 compatible = "st,stm32-timers";
146 reg = <0x40000800 0x400>;
147 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
152 compatible = "st,stm32-pwm";
157 compatible = "st,stm32-timer-trigger";
163 timer5: timer@40000c00 {
164 compatible = "st,stm32-timer";
165 reg = <0x40000c00 0x400>;
167 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
170 timers5: timers@40000c00 {
171 #address-cells = <1>;
173 compatible = "st,stm32-timers";
174 reg = <0x40000C00 0x400>;
175 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
180 compatible = "st,stm32-pwm";
185 compatible = "st,stm32-timer-trigger";
191 timer6: timer@40001000 {
192 compatible = "st,stm32-timer";
193 reg = <0x40001000 0x400>;
195 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
199 timers6: timers@40001000 {
200 #address-cells = <1>;
202 compatible = "st,stm32-timers";
203 reg = <0x40001000 0x400>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
209 compatible = "st,stm32-timer-trigger";
215 timer7: timer@40001400 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001400 0x400>;
219 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
223 timers7: timers@40001400 {
224 #address-cells = <1>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001400 0x400>;
228 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
233 compatible = "st,stm32-timer-trigger";
239 timers12: timers@40001800 {
240 #address-cells = <1>;
242 compatible = "st,stm32-timers";
243 reg = <0x40001800 0x400>;
244 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
249 compatible = "st,stm32-pwm";
254 compatible = "st,stm32-timer-trigger";
260 timers13: timers@40001c00 {
261 #address-cells = <1>;
263 compatible = "st,stm32-timers";
264 reg = <0x40001C00 0x400>;
265 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
270 compatible = "st,stm32-pwm";
275 timers14: timers@40002000 {
276 #address-cells = <1>;
278 compatible = "st,stm32-timers";
279 reg = <0x40002000 0x400>;
280 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
285 compatible = "st,stm32-pwm";
291 compatible = "st,stm32-rtc";
292 reg = <0x40002800 0x400>;
293 clocks = <&rcc 1 CLK_RTC>;
294 clock-names = "ck_rtc";
295 assigned-clocks = <&rcc 1 CLK_RTC>;
296 assigned-clock-parents = <&rcc 1 CLK_LSE>;
297 interrupt-parent = <&exti>;
299 interrupt-names = "alarm";
300 st,syscfg = <&pwrcfg 0x00 0x100>;
304 usart2: serial@40004400 {
305 compatible = "st,stm32f7-uart";
306 reg = <0x40004400 0x400>;
308 clocks = <&rcc 1 CLK_USART2>;
312 usart3: serial@40004800 {
313 compatible = "st,stm32f7-uart";
314 reg = <0x40004800 0x400>;
316 clocks = <&rcc 1 CLK_USART3>;
320 usart4: serial@40004c00 {
321 compatible = "st,stm32f7-uart";
322 reg = <0x40004c00 0x400>;
324 clocks = <&rcc 1 CLK_UART4>;
328 usart5: serial@40005000 {
329 compatible = "st,stm32f7-uart";
330 reg = <0x40005000 0x400>;
332 clocks = <&rcc 1 CLK_UART5>;
337 compatible = "st,stm32f7-i2c";
338 reg = <0x40005400 0x400>;
341 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
342 clocks = <&rcc 1 CLK_I2C1>;
343 #address-cells = <1>;
349 compatible = "st,stm32f7-i2c";
350 reg = <0x40005800 0x400>;
353 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
354 clocks = <&rcc 1 CLK_I2C2>;
355 #address-cells = <1>;
361 compatible = "st,stm32f7-i2c";
362 reg = <0x40005C00 0x400>;
365 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
366 clocks = <&rcc 1 CLK_I2C3>;
367 #address-cells = <1>;
373 compatible = "st,stm32f7-i2c";
374 reg = <0x40006000 0x400>;
377 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
378 clocks = <&rcc 1 CLK_I2C4>;
379 #address-cells = <1>;
385 compatible = "st,stm32-cec";
386 reg = <0x40006C00 0x400>;
388 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
389 clock-names = "cec", "hdmi-cec";
393 usart7: serial@40007800 {
394 compatible = "st,stm32f7-uart";
395 reg = <0x40007800 0x400>;
397 clocks = <&rcc 1 CLK_UART7>;
401 usart8: serial@40007c00 {
402 compatible = "st,stm32f7-uart";
403 reg = <0x40007c00 0x400>;
405 clocks = <&rcc 1 CLK_UART8>;
409 timers1: timers@40010000 {
410 #address-cells = <1>;
412 compatible = "st,stm32-timers";
413 reg = <0x40010000 0x400>;
414 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
419 compatible = "st,stm32-pwm";
424 compatible = "st,stm32-timer-trigger";
430 timers8: timers@40010400 {
431 #address-cells = <1>;
433 compatible = "st,stm32-timers";
434 reg = <0x40010400 0x400>;
435 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
440 compatible = "st,stm32-pwm";
445 compatible = "st,stm32-timer-trigger";
451 usart1: serial@40011000 {
452 compatible = "st,stm32f7-uart";
453 reg = <0x40011000 0x400>;
455 clocks = <&rcc 1 CLK_USART1>;
459 usart6: serial@40011400 {
460 compatible = "st,stm32f7-uart";
461 reg = <0x40011400 0x400>;
463 clocks = <&rcc 1 CLK_USART6>;
467 sdio2: sdio2@40011c00 {
468 compatible = "arm,pl180", "arm,primecell";
469 arm,primecell-periphid = <0x00880180>;
470 reg = <0x40011c00 0x400>;
471 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
472 clock-names = "apb_pclk";
474 max-frequency = <48000000>;
478 sdio1: sdio1@40012c00 {
479 compatible = "arm,pl180", "arm,primecell";
480 arm,primecell-periphid = <0x00880180>;
481 reg = <0x40012c00 0x400>;
482 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
483 clock-names = "apb_pclk";
485 max-frequency = <48000000>;
489 syscfg: system-config@40013800 {
490 compatible = "syscon";
491 reg = <0x40013800 0x400>;
494 exti: interrupt-controller@40013c00 {
495 compatible = "st,stm32-exti";
496 interrupt-controller;
497 #interrupt-cells = <2>;
498 reg = <0x40013C00 0x400>;
499 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
502 timers9: timers@40014000 {
503 #address-cells = <1>;
505 compatible = "st,stm32-timers";
506 reg = <0x40014000 0x400>;
507 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
512 compatible = "st,stm32-pwm";
517 compatible = "st,stm32-timer-trigger";
523 timers10: timers@40014400 {
524 #address-cells = <1>;
526 compatible = "st,stm32-timers";
527 reg = <0x40014400 0x400>;
528 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
533 compatible = "st,stm32-pwm";
538 timers11: timers@40014800 {
539 #address-cells = <1>;
541 compatible = "st,stm32-timers";
542 reg = <0x40014800 0x400>;
543 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
548 compatible = "st,stm32-pwm";
553 pwrcfg: power-config@40007000 {
554 compatible = "syscon";
555 reg = <0x40007000 0x400>;
559 compatible = "st,stm32f7-crc";
560 reg = <0x40023000 0x400>;
561 clocks = <&rcc 0 12>;
568 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
569 reg = <0x40023800 0x400>;
570 clocks = <&clk_hse>, <&clk_i2s_ckin>;
571 st,syscfg = <&pwrcfg>;
572 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
573 assigned-clock-rates = <1000000>;
577 compatible = "st,stm32-dma";
578 reg = <0x40026000 0x400>;
587 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
593 compatible = "st,stm32-dma";
594 reg = <0x40026400 0x400>;
603 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
609 usbotg_hs: usb@40040000 {
610 compatible = "st,stm32f7-hsotg";
611 reg = <0x40040000 0x40000>;
613 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
615 g-rx-fifo-size = <256>;
616 g-np-tx-fifo-size = <32>;
617 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
621 usbotg_fs: usb@50000000 {
622 compatible = "st,stm32f4x9-fsotg";
623 reg = <0x50000000 0x40000>;
625 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;