arch/arm/dts/stm32f7-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <dt-bindings/memory/stm32-sdram.h>
   4 /{
   5         soc {
   6                 u-boot,dm-pre-reloc;
   7
   8                 fmc: fmc@A0000000 {
   9                         compatible = "st,stm32-fmc";
  10                         reg = <0xA0000000 0x1000>;
  11                         clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
  12                         pinctrl-0 = <&fmc_pins>;
  13                         pinctrl-names = "default";
  14                         status = "okay";
  15                         u-boot,dm-pre-reloc;
  16                 };
  17
  18                 mac: ethernet@40028000 {
  19                         compatible = "st,stm32-dwmac";
  20                         reg = <0x40028000 0x8000>;
  21                         reg-names = "stmmaceth";
  22                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
  23                                  <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
  24                                  <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
  25                         interrupts = <61>, <62>;
  26                         interrupt-names = "macirq", "eth_wake_irq";
  27                         snps,pbl = <8>;
  28                         snps,mixed-burst;
  29                         dma-ranges;
  30                         pinctrl-0 = <&ethernet_mii>;
  31                         phy-mode = "rmii";
  32                         phy-handle = <&phy0>;
  33
  34                         status = "okay";
  35
  36                         mdio0 {
  37                                 #address-cells = <1>;
  38                                 #size-cells = <0>;
  39                                 compatible = "snps,dwmac-mdio";
  40                                 phy0: ethernet-phy@0 {
  41                                         reg = <0>;
  42                                 };
  43                         };
  44                 };
  45
  46                 qspi: quadspi@A0001000 {
  47                         compatible = "st,stm32-qspi";
  48                         #address-cells = <1>;
  49                         #size-cells = <0>;
  50                         reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
  51                         reg-names = "qspi", "qspi_mm";
  52                         interrupts = <92>;
  53                         spi-max-frequency = <108000000>;
  54                         clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
  55                         resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
  56                         pinctrl-0 = <&qspi_pins>;
  57
  58                         status = "okay";
  59                 };
  60         };
  61 };
  62
  63 &clk_hse {
  64         u-boot,dm-pre-reloc;
  65 };
  66
  67 &gpioa {
  68         compatible = "st,stm32-gpio";
  69         u-boot,dm-pre-reloc;
  70 };
  71
  72 &gpiob {
  73         compatible = "st,stm32-gpio";
  74         u-boot,dm-pre-reloc;
  75 };
  76
  77 &gpioc {
  78         compatible = "st,stm32-gpio";
  79         u-boot,dm-pre-reloc;
  80 };
  81
  82 &gpiod {
  83         compatible = "st,stm32-gpio";
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &gpioe {
  88         compatible = "st,stm32-gpio";
  89         u-boot,dm-pre-reloc;
  90 };
  91
  92 &gpiof {
  93         compatible = "st,stm32-gpio";
  94         u-boot,dm-pre-reloc;
  95 };
  96
  97 &gpiog {
  98         compatible = "st,stm32-gpio";
  99         u-boot,dm-pre-reloc;
 100 };
 101
 102 &gpioh {
 103         compatible = "st,stm32-gpio";
 104         u-boot,dm-pre-reloc;
 105 };
 106
 107 &gpioi {
 108         compatible = "st,stm32-gpio";
 109         u-boot,dm-pre-reloc;
 110 };
 111
 112 &gpioj {
 113         compatible = "st,stm32-gpio";
 114 };
 115
 116 &gpiok {
 117         compatible = "st,stm32-gpio";
 118 };
 119
 120 &pinctrl {
 121         u-boot,dm-pre-reloc;
 122
 123         fmc_pins: fmc@0 {
 124                 u-boot,dm-pre-reloc;
 125                 pins
 126                 {
 127                  u-boot,dm-pre-reloc;
 128                 };
 129         };
 130 };
 131
 132 &pwrcfg {
 133         u-boot,dm-pre-reloc;
 134 };
 135
 136 &rcc {
 137         u-boot,dm-pre-reloc;
 138 };
 139
 140 &timer5 {
 141         u-boot,dm-pre-reloc;
 142 };
 143
 144 &usart1 {
 145         u-boot,dm-pre-reloc;
 146         clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
 147 };