arch/arm/dts/stm32f7-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 /{
   4         soc {
   5                 u-boot,dm-pre-reloc;
   6
   7                 fmc: fmc@A0000000 {
   8                         compatible = "st,stm32-fmc";
   9                         reg = <0xA0000000 0x1000>;
  10                         clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
  11                         pinctrl-0 = <&fmc_pins>;
  12                         pinctrl-names = "default";
  13                         status = "okay";
  14                         u-boot,dm-pre-reloc;
  15                 };
  16
  17                 mac: ethernet@40028000 {
  18                         compatible = "st,stm32-dwmac";
  19                         reg = <0x40028000 0x8000>;
  20                         reg-names = "stmmaceth";
  21                         clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
  22                                  <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
  23                                  <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
  24                         interrupts = <61>, <62>;
  25                         interrupt-names = "macirq", "eth_wake_irq";
  26                         snps,pbl = <8>;
  27                         snps,mixed-burst;
  28                         dma-ranges;
  29                         pinctrl-0 = <&ethernet_mii>;
  30                         phy-mode = "rmii";
  31                         phy-handle = <&phy0>;
  32
  33                         status = "okay";
  34
  35                         mdio0 {
  36                                 #address-cells = <1>;
  37                                 #size-cells = <0>;
  38                                 compatible = "snps,dwmac-mdio";
  39                                 phy0: ethernet-phy@0 {
  40                                         reg = <0>;
  41                                 };
  42                         };
  43                 };
  44
  45                 qspi: quadspi@A0001000 {
  46                         compatible = "st,stm32-qspi";
  47                         #address-cells = <1>;
  48                         #size-cells = <0>;
  49                         reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
  50                         reg-names = "qspi", "qspi_mm";
  51                         interrupts = <92>;
  52                         spi-max-frequency = <108000000>;
  53                         clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
  54                         resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
  55                         pinctrl-0 = <&qspi_pins>;
  56
  57                         status = "okay";
  58                 };
  59         };
  60 };
  61
  62 &clk_hse {
  63         u-boot,dm-pre-reloc;
  64 };
  65
  66 &gpioa {
  67         compatible = "st,stm32-gpio";
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 &gpiob {
  72         compatible = "st,stm32-gpio";
  73         u-boot,dm-pre-reloc;
  74 };
  75
  76 &gpioc {
  77         compatible = "st,stm32-gpio";
  78         u-boot,dm-pre-reloc;
  79 };
  80
  81 &gpiod {
  82         compatible = "st,stm32-gpio";
  83         u-boot,dm-pre-reloc;
  84 };
  85
  86 &gpioe {
  87         compatible = "st,stm32-gpio";
  88         u-boot,dm-pre-reloc;
  89 };
  90
  91 &gpiof {
  92         compatible = "st,stm32-gpio";
  93         u-boot,dm-pre-reloc;
  94 };
  95
  96 &gpiog {
  97         compatible = "st,stm32-gpio";
  98         u-boot,dm-pre-reloc;
  99 };
 100
 101 &gpioh {
 102         compatible = "st,stm32-gpio";
 103         u-boot,dm-pre-reloc;
 104 };
 105
 106 &gpioi {
 107         compatible = "st,stm32-gpio";
 108         u-boot,dm-pre-reloc;
 109 };
 110
 111 &gpioj {
 112         compatible = "st,stm32-gpio";
 113 };
 114
 115 &gpiok {
 116         compatible = "st,stm32-gpio";
 117 };
 118
 119 &pinctrl {
 120         u-boot,dm-pre-reloc;
 121
 122         fmc_pins: fmc@0 {
 123                 u-boot,dm-pre-reloc;
 124                 pins
 125                 {
 126                  u-boot,dm-pre-reloc;
 127                 };
 128         };
 129
 130         usart1_pins_a: usart1@0 {
 131                 u-boot,dm-pre-reloc;
 132                 pins1 {
 133                         u-boot,dm-pre-reloc;
 134                 };
 135                 pins2 {
 136                         u-boot,dm-pre-reloc;
 137                 };
 138         };
 139 };
 140
 141 &pwrcfg {
 142         u-boot,dm-pre-reloc;
 143 };
 144
 145 &rcc {
 146         u-boot,dm-pre-reloc;
 147 };
 148
 149 &timer5 {
 150         u-boot,dm-pre-reloc;
 151 };
 152
 153 &usart1 {
 154         u-boot,dm-pre-reloc;
 155 };