1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
7 #include <dt-bindings/memory/stm32-sdram.h>
14 /* Aliases for gpios so as to use sequence */
35 compatible = "st,stm32-fmc";
36 reg = <0xA0000000 0x1000>;
37 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
38 st,syscfg = <&syscfg>;
39 pinctrl-0 = <&fmc_pins_d32>;
40 pinctrl-names = "default";
45 * Memory configuration from sdram
46 * MICRON MT48LC4M32B2B5-6A
49 st,sdram-control = /bits/ 8 <NO_COL_8
57 st,sdram-timing = /bits/ 8 <TMRD_2
64 st,sdram-refcount = < 1292 >;
95 compatible = "st,stm32-gpio";
100 compatible = "st,stm32-gpio";
105 compatible = "st,stm32-gpio";
110 compatible = "st,stm32-gpio";
115 compatible = "st,stm32-gpio";
120 compatible = "st,stm32-gpio";
125 compatible = "st,stm32-gpio";
130 compatible = "st,stm32-gpio";
135 compatible = "st,stm32-gpio";
140 compatible = "st,stm32-gpio";
145 compatible = "st,stm32-gpio";
150 usart3_pins_a: usart3@0 {
160 fmc_pins_d32: fmc_d32@0 {
164 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
165 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
166 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
167 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
168 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
169 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
170 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
171 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
172 <STM32_PINMUX('H',15, AF12)>, /* D23 */
173 <STM32_PINMUX('H',14, AF12)>, /* D22 */
174 <STM32_PINMUX('H',13, AF12)>, /* D21 */
175 <STM32_PINMUX('H',12, AF12)>, /* D20 */
176 <STM32_PINMUX('H',11, AF12)>, /* D19 */
177 <STM32_PINMUX('H',10, AF12)>, /* D18 */
178 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
179 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
181 <STM32_PINMUX('D',10, AF12)>, /* D15 */
182 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
183 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
184 <STM32_PINMUX('E',15, AF12)>, /* D12 */
185 <STM32_PINMUX('E',14, AF12)>, /* D11 */
186 <STM32_PINMUX('E',13, AF12)>, /* D10 */
187 <STM32_PINMUX('E',12, AF12)>, /* D09 */
188 <STM32_PINMUX('E',11, AF12)>, /* D08 */
189 <STM32_PINMUX('E',10, AF12)>, /* D07 */
190 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
191 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
192 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
193 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
194 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
195 <STM32_PINMUX('D',15, AF12)>, /* D01 */
196 <STM32_PINMUX('D',14, AF12)>, /* D00 */
198 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
199 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
200 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
201 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
203 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
204 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
206 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
207 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
208 <STM32_PINMUX('F',15, AF12)>, /* A09 */
209 <STM32_PINMUX('F',14, AF12)>, /* A08 */
210 <STM32_PINMUX('F',13, AF12)>, /* A07 */
211 <STM32_PINMUX('F',12, AF12)>, /* A06 */
212 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
213 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
214 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
215 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
216 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
217 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
219 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
220 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
221 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
222 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
223 <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
224 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */