1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
7 #include "armv7-m.dtsi"
8 #include <dt-bindings/clock/stm32fx-clock.h>
9 #include <dt-bindings/mfd/stm32f4-rcc.h>
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
30 compatible = "fixed-clock";
31 clock-frequency = <32000>;
34 clk_i2s_ckin: i2s-ckin {
36 compatible = "fixed-clock";
37 clock-frequency = <0>;
42 romem: nvmem@1fff7800 {
43 compatible = "st,stm32f4-otp";
44 reg = <0x1fff7800 0x400>;
55 timer2: timer@40000000 {
56 compatible = "st,stm32-timer";
57 reg = <0x40000000 0x400>;
59 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
63 timers2: timers@40000000 {
66 compatible = "st,stm32-timers";
67 reg = <0x40000000 0x400>;
68 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
73 compatible = "st,stm32-pwm";
79 compatible = "st,stm32-timer-trigger";
85 timer3: timer@40000400 {
86 compatible = "st,stm32-timer";
87 reg = <0x40000400 0x400>;
89 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
93 timers3: timers@40000400 {
96 compatible = "st,stm32-timers";
97 reg = <0x40000400 0x400>;
98 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
103 compatible = "st,stm32-pwm";
109 compatible = "st,stm32-timer-trigger";
115 timer4: timer@40000800 {
116 compatible = "st,stm32-timer";
117 reg = <0x40000800 0x400>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
123 timers4: timers@40000800 {
124 #address-cells = <1>;
126 compatible = "st,stm32-timers";
127 reg = <0x40000800 0x400>;
128 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
133 compatible = "st,stm32-pwm";
139 compatible = "st,stm32-timer-trigger";
145 timer5: timer@40000c00 {
146 compatible = "st,stm32-timer";
147 reg = <0x40000c00 0x400>;
149 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
152 timers5: timers@40000c00 {
153 #address-cells = <1>;
155 compatible = "st,stm32-timers";
156 reg = <0x40000C00 0x400>;
157 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
162 compatible = "st,stm32-pwm";
168 compatible = "st,stm32-timer-trigger";
174 timer6: timer@40001000 {
175 compatible = "st,stm32-timer";
176 reg = <0x40001000 0x400>;
178 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
182 timers6: timers@40001000 {
183 #address-cells = <1>;
185 compatible = "st,stm32-timers";
186 reg = <0x40001000 0x400>;
187 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
192 compatible = "st,stm32-timer-trigger";
198 timer7: timer@40001400 {
199 compatible = "st,stm32-timer";
200 reg = <0x40001400 0x400>;
202 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
206 timers7: timers@40001400 {
207 #address-cells = <1>;
209 compatible = "st,stm32-timers";
210 reg = <0x40001400 0x400>;
211 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
216 compatible = "st,stm32-timer-trigger";
222 timers12: timers@40001800 {
223 #address-cells = <1>;
225 compatible = "st,stm32-timers";
226 reg = <0x40001800 0x400>;
227 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
232 compatible = "st,stm32-pwm";
238 compatible = "st,stm32-timer-trigger";
244 timers13: timers@40001c00 {
245 #address-cells = <1>;
247 compatible = "st,stm32-timers";
248 reg = <0x40001C00 0x400>;
249 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
254 compatible = "st,stm32-pwm";
260 timers14: timers@40002000 {
261 #address-cells = <1>;
263 compatible = "st,stm32-timers";
264 reg = <0x40002000 0x400>;
265 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
270 compatible = "st,stm32-pwm";
277 compatible = "st,stm32-rtc";
278 reg = <0x40002800 0x400>;
279 clocks = <&rcc 1 CLK_RTC>;
280 clock-names = "ck_rtc";
281 assigned-clocks = <&rcc 1 CLK_RTC>;
282 assigned-clock-parents = <&rcc 1 CLK_LSE>;
283 interrupt-parent = <&exti>;
285 interrupt-names = "alarm";
286 st,syscfg = <&pwrcfg 0x00 0x100>;
290 iwdg: watchdog@40003000 {
291 compatible = "st,stm32-iwdg";
292 reg = <0x40003000 0x400>;
299 #address-cells = <1>;
301 compatible = "st,stm32f4-spi";
302 reg = <0x40003800 0x400>;
304 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
309 #address-cells = <1>;
311 compatible = "st,stm32f4-spi";
312 reg = <0x40003c00 0x400>;
314 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
318 usart2: serial@40004400 {
319 compatible = "st,stm32-uart";
320 reg = <0x40004400 0x400>;
322 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
326 usart3: serial@40004800 {
327 compatible = "st,stm32-uart";
328 reg = <0x40004800 0x400>;
330 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
332 dmas = <&dma1 1 4 0x400 0x0>,
333 <&dma1 3 4 0x400 0x0>;
334 dma-names = "rx", "tx";
337 usart4: serial@40004c00 {
338 compatible = "st,stm32-uart";
339 reg = <0x40004c00 0x400>;
341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
345 usart5: serial@40005000 {
346 compatible = "st,stm32-uart";
347 reg = <0x40005000 0x400>;
349 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
354 compatible = "st,stm32f4-i2c";
355 reg = <0x40005400 0x400>;
358 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
360 #address-cells = <1>;
366 compatible = "st,stm32f4-dac-core";
367 reg = <0x40007400 0x400>;
368 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
370 clock-names = "pclk";
371 #address-cells = <1>;
376 compatible = "st,stm32-dac";
377 #io-channels-cells = <1>;
383 compatible = "st,stm32-dac";
384 #io-channels-cells = <1>;
390 usart7: serial@40007800 {
391 compatible = "st,stm32-uart";
392 reg = <0x40007800 0x400>;
394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
398 usart8: serial@40007c00 {
399 compatible = "st,stm32-uart";
400 reg = <0x40007c00 0x400>;
402 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
406 timers1: timers@40010000 {
407 #address-cells = <1>;
409 compatible = "st,stm32-timers";
410 reg = <0x40010000 0x400>;
411 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
416 compatible = "st,stm32-pwm";
422 compatible = "st,stm32-timer-trigger";
428 timers8: timers@40010400 {
429 #address-cells = <1>;
431 compatible = "st,stm32-timers";
432 reg = <0x40010400 0x400>;
433 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
438 compatible = "st,stm32-pwm";
444 compatible = "st,stm32-timer-trigger";
450 usart1: serial@40011000 {
451 compatible = "st,stm32-uart";
452 reg = <0x40011000 0x400>;
454 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
456 dmas = <&dma2 2 4 0x400 0x0>,
457 <&dma2 7 4 0x400 0x0>;
458 dma-names = "rx", "tx";
461 usart6: serial@40011400 {
462 compatible = "st,stm32-uart";
463 reg = <0x40011400 0x400>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
470 compatible = "st,stm32f4-adc-core";
471 reg = <0x40012000 0x400>;
473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
475 interrupt-controller;
476 #interrupt-cells = <1>;
477 #address-cells = <1>;
482 compatible = "st,stm32f4-adc";
483 #io-channel-cells = <1>;
485 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
486 interrupt-parent = <&adc>;
488 dmas = <&dma2 0 0 0x400 0x0>;
494 compatible = "st,stm32f4-adc";
495 #io-channel-cells = <1>;
497 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
498 interrupt-parent = <&adc>;
500 dmas = <&dma2 3 1 0x400 0x0>;
506 compatible = "st,stm32f4-adc";
507 #io-channel-cells = <1>;
509 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
510 interrupt-parent = <&adc>;
512 dmas = <&dma2 1 2 0x400 0x0>;
518 sdio: sdio@40012c00 {
519 compatible = "arm,pl180", "arm,primecell";
520 arm,primecell-periphid = <0x00880180>;
521 reg = <0x40012c00 0x400>;
522 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
523 clock-names = "apb_pclk";
525 max-frequency = <48000000>;
530 #address-cells = <1>;
532 compatible = "st,stm32f4-spi";
533 reg = <0x40013000 0x400>;
535 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
540 #address-cells = <1>;
542 compatible = "st,stm32f4-spi";
543 reg = <0x40013400 0x400>;
545 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
549 syscfg: system-config@40013800 {
550 compatible = "syscon";
551 reg = <0x40013800 0x400>;
554 exti: interrupt-controller@40013c00 {
555 compatible = "st,stm32-exti";
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 reg = <0x40013C00 0x400>;
559 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
562 timers9: timers@40014000 {
563 #address-cells = <1>;
565 compatible = "st,stm32-timers";
566 reg = <0x40014000 0x400>;
567 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
572 compatible = "st,stm32-pwm";
578 compatible = "st,stm32-timer-trigger";
584 timers10: timers@40014400 {
585 #address-cells = <1>;
587 compatible = "st,stm32-timers";
588 reg = <0x40014400 0x400>;
589 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
594 compatible = "st,stm32-pwm";
600 timers11: timers@40014800 {
601 #address-cells = <1>;
603 compatible = "st,stm32-timers";
604 reg = <0x40014800 0x400>;
605 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
610 compatible = "st,stm32-pwm";
617 #address-cells = <1>;
619 compatible = "st,stm32f4-spi";
620 reg = <0x40015000 0x400>;
622 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
627 #address-cells = <1>;
629 compatible = "st,stm32f4-spi";
630 reg = <0x40015400 0x400>;
632 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
636 pwrcfg: power-config@40007000 {
637 compatible = "syscon";
638 reg = <0x40007000 0x400>;
641 ltdc: display-controller@40016800 {
642 compatible = "st,stm32-ltdc";
643 reg = <0x40016800 0x200>;
644 interrupts = <88>, <89>;
645 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
646 clocks = <&rcc 1 CLK_LCD>;
652 compatible = "st,stm32f4-crc";
653 reg = <0x40023000 0x400>;
654 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
661 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
662 reg = <0x40023800 0x400>;
663 clocks = <&clk_hse>, <&clk_i2s_ckin>;
664 st,syscfg = <&pwrcfg>;
665 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
666 assigned-clock-rates = <1000000>;
669 dma1: dma-controller@40026000 {
670 compatible = "st,stm32-dma";
671 reg = <0x40026000 0x400>;
680 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
684 dma2: dma-controller@40026400 {
685 compatible = "st,stm32-dma";
686 reg = <0x40026400 0x400>;
695 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
700 mac: ethernet@40028000 {
701 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
702 reg = <0x40028000 0x8000>;
703 reg-names = "stmmaceth";
705 interrupt-names = "macirq";
706 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
707 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
708 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
709 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
710 st,syscon = <&syscfg 0x4>;
716 usbotg_hs: usb@40040000 {
717 compatible = "snps,dwc2";
718 reg = <0x40040000 0x40000>;
720 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
725 usbotg_fs: usb@50000000 {
726 compatible = "st,stm32f4x9-fsotg";
727 reg = <0x50000000 0x40000>;
729 clocks = <&rcc 0 39>;
734 dcmi: dcmi@50050000 {
735 compatible = "st,stm32-dcmi";
736 reg = <0x50050000 0x400>;
738 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
739 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
740 clock-names = "mclk";
741 pinctrl-names = "default";
742 pinctrl-0 = <&dcmi_pins>;
743 dmas = <&dma2 1 1 0x414 0x3>;
749 compatible = "st,stm32-rng";
750 reg = <0x50060800 0x400>;
752 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
759 clocks = <&rcc 1 SYSTICK>;