2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/clock/stm32fx-clock.h>
46 #include <dt-bindings/mfd/stm32f4-rcc.h>
52 compatible = "fixed-clock";
53 clock-frequency = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
64 compatible = "fixed-clock";
65 clock-frequency = <32000>;
68 clk_i2s_ckin: i2s-ckin {
70 compatible = "fixed-clock";
71 clock-frequency = <0>;
76 timer2: timer@40000000 {
77 compatible = "st,stm32-timer";
78 reg = <0x40000000 0x400>;
80 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
84 timers2: timers@40000000 {
87 compatible = "st,stm32-timers";
88 reg = <0x40000000 0x400>;
89 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
94 compatible = "st,stm32-pwm";
99 compatible = "st,stm32-timer-trigger";
105 timer3: timer@40000400 {
106 compatible = "st,stm32-timer";
107 reg = <0x40000400 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
113 timers3: timers@40000400 {
114 #address-cells = <1>;
116 compatible = "st,stm32-timers";
117 reg = <0x40000400 0x400>;
118 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
123 compatible = "st,stm32-pwm";
128 compatible = "st,stm32-timer-trigger";
134 timer4: timer@40000800 {
135 compatible = "st,stm32-timer";
136 reg = <0x40000800 0x400>;
138 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
142 timers4: timers@40000800 {
143 #address-cells = <1>;
145 compatible = "st,stm32-timers";
146 reg = <0x40000800 0x400>;
147 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
152 compatible = "st,stm32-pwm";
157 compatible = "st,stm32-timer-trigger";
163 timer5: timer@40000c00 {
164 compatible = "st,stm32-timer";
165 reg = <0x40000c00 0x400>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
170 timers5: timers@40000c00 {
171 #address-cells = <1>;
173 compatible = "st,stm32-timers";
174 reg = <0x40000C00 0x400>;
175 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
180 compatible = "st,stm32-pwm";
185 compatible = "st,stm32-timer-trigger";
191 timer6: timer@40001000 {
192 compatible = "st,stm32-timer";
193 reg = <0x40001000 0x400>;
195 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
199 timers6: timers@40001000 {
200 #address-cells = <1>;
202 compatible = "st,stm32-timers";
203 reg = <0x40001000 0x400>;
204 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
209 compatible = "st,stm32-timer-trigger";
215 timer7: timer@40001400 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001400 0x400>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
223 timers7: timers@40001400 {
224 #address-cells = <1>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001400 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
233 compatible = "st,stm32-timer-trigger";
239 timers12: timers@40001800 {
240 #address-cells = <1>;
242 compatible = "st,stm32-timers";
243 reg = <0x40001800 0x400>;
244 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
249 compatible = "st,stm32-pwm";
254 compatible = "st,stm32-timer-trigger";
260 timers13: timers@40001c00 {
261 #address-cells = <1>;
263 compatible = "st,stm32-timers";
264 reg = <0x40001C00 0x400>;
265 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
270 compatible = "st,stm32-pwm";
275 timers14: timers@40002000 {
276 #address-cells = <1>;
278 compatible = "st,stm32-timers";
279 reg = <0x40002000 0x400>;
280 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
285 compatible = "st,stm32-pwm";
291 compatible = "st,stm32-rtc";
292 reg = <0x40002800 0x400>;
293 clocks = <&rcc 1 CLK_RTC>;
294 clock-names = "ck_rtc";
295 assigned-clocks = <&rcc 1 CLK_RTC>;
296 assigned-clock-parents = <&rcc 1 CLK_LSE>;
297 interrupt-parent = <&exti>;
299 interrupt-names = "alarm";
300 st,syscfg = <&pwrcfg 0x00 0x100>;
304 iwdg: watchdog@40003000 {
305 compatible = "st,stm32-iwdg";
306 reg = <0x40003000 0x400>;
312 usart2: serial@40004400 {
313 compatible = "st,stm32-uart";
314 reg = <0x40004400 0x400>;
316 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
320 usart3: serial@40004800 {
321 compatible = "st,stm32-uart";
322 reg = <0x40004800 0x400>;
324 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
326 dmas = <&dma1 1 4 0x400 0x0>,
327 <&dma1 3 4 0x400 0x0>;
328 dma-names = "rx", "tx";
331 usart4: serial@40004c00 {
332 compatible = "st,stm32-uart";
333 reg = <0x40004c00 0x400>;
335 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
339 usart5: serial@40005000 {
340 compatible = "st,stm32-uart";
341 reg = <0x40005000 0x400>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
348 compatible = "st,stm32f4-i2c";
349 reg = <0x40005400 0x400>;
352 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
354 #address-cells = <1>;
360 compatible = "st,stm32f4-dac-core";
361 reg = <0x40007400 0x400>;
362 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
363 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
364 clock-names = "pclk";
365 #address-cells = <1>;
370 compatible = "st,stm32-dac";
371 #io-channels-cells = <1>;
377 compatible = "st,stm32-dac";
378 #io-channels-cells = <1>;
384 usart7: serial@40007800 {
385 compatible = "st,stm32-uart";
386 reg = <0x40007800 0x400>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
392 usart8: serial@40007c00 {
393 compatible = "st,stm32-uart";
394 reg = <0x40007c00 0x400>;
396 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
400 timers1: timers@40010000 {
401 #address-cells = <1>;
403 compatible = "st,stm32-timers";
404 reg = <0x40010000 0x400>;
405 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
410 compatible = "st,stm32-pwm";
415 compatible = "st,stm32-timer-trigger";
421 timers8: timers@40010400 {
422 #address-cells = <1>;
424 compatible = "st,stm32-timers";
425 reg = <0x40010400 0x400>;
426 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
431 compatible = "st,stm32-pwm";
436 compatible = "st,stm32-timer-trigger";
442 usart1: serial@40011000 {
443 compatible = "st,stm32-uart";
444 reg = <0x40011000 0x400>;
446 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
448 dmas = <&dma2 2 4 0x400 0x0>,
449 <&dma2 7 4 0x400 0x0>;
450 dma-names = "rx", "tx";
453 usart6: serial@40011400 {
454 compatible = "st,stm32-uart";
455 reg = <0x40011400 0x400>;
457 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
462 compatible = "st,stm32f4-adc-core";
463 reg = <0x40012000 0x400>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
467 interrupt-controller;
468 #interrupt-cells = <1>;
469 #address-cells = <1>;
474 compatible = "st,stm32f4-adc";
475 #io-channel-cells = <1>;
477 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
478 interrupt-parent = <&adc>;
480 dmas = <&dma2 0 0 0x400 0x0>;
486 compatible = "st,stm32f4-adc";
487 #io-channel-cells = <1>;
489 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
490 interrupt-parent = <&adc>;
492 dmas = <&dma2 3 1 0x400 0x0>;
498 compatible = "st,stm32f4-adc";
499 #io-channel-cells = <1>;
501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
502 interrupt-parent = <&adc>;
504 dmas = <&dma2 1 2 0x400 0x0>;
510 sdio: sdio@40012c00 {
511 compatible = "arm,pl180", "arm,primecell";
512 arm,primecell-periphid = <0x00880180>;
513 reg = <0x40012c00 0x400>;
514 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
515 clock-names = "apb_pclk";
517 max-frequency = <48000000>;
521 syscfg: system-config@40013800 {
522 compatible = "syscon";
523 reg = <0x40013800 0x400>;
526 exti: interrupt-controller@40013c00 {
527 compatible = "st,stm32-exti";
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 reg = <0x40013C00 0x400>;
531 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
534 timers9: timers@40014000 {
535 #address-cells = <1>;
537 compatible = "st,stm32-timers";
538 reg = <0x40014000 0x400>;
539 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
544 compatible = "st,stm32-pwm";
549 compatible = "st,stm32-timer-trigger";
555 timers10: timers@40014400 {
556 #address-cells = <1>;
558 compatible = "st,stm32-timers";
559 reg = <0x40014400 0x400>;
560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
565 compatible = "st,stm32-pwm";
570 timers11: timers@40014800 {
571 #address-cells = <1>;
573 compatible = "st,stm32-timers";
574 reg = <0x40014800 0x400>;
575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
580 compatible = "st,stm32-pwm";
585 pwrcfg: power-config@40007000 {
586 compatible = "syscon";
587 reg = <0x40007000 0x400>;
590 ltdc: display-controller@40016800 {
591 compatible = "st,stm32-ltdc";
592 reg = <0x40016800 0x200>;
593 interrupts = <88>, <89>;
594 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
595 clocks = <&rcc 1 CLK_LCD>;
601 compatible = "st,stm32f4-crc";
602 reg = <0x40023000 0x400>;
603 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
610 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
611 reg = <0x40023800 0x400>;
612 clocks = <&clk_hse>, <&clk_i2s_ckin>;
613 st,syscfg = <&pwrcfg>;
614 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
615 assigned-clock-rates = <1000000>;
618 dma1: dma-controller@40026000 {
619 compatible = "st,stm32-dma";
620 reg = <0x40026000 0x400>;
629 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
633 dma2: dma-controller@40026400 {
634 compatible = "st,stm32-dma";
635 reg = <0x40026400 0x400>;
644 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
649 mac: ethernet@40028000 {
650 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
651 reg = <0x40028000 0x8000>;
652 reg-names = "stmmaceth";
654 interrupt-names = "macirq";
655 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
656 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
657 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
658 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
659 st,syscon = <&syscfg 0x4>;
665 usbotg_hs: usb@40040000 {
666 compatible = "snps,dwc2";
667 reg = <0x40040000 0x40000>;
669 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
674 usbotg_fs: usb@50000000 {
675 compatible = "st,stm32f4x9-fsotg";
676 reg = <0x50000000 0x40000>;
678 clocks = <&rcc 0 39>;
683 dcmi: dcmi@50050000 {
684 compatible = "st,stm32-dcmi";
685 reg = <0x50050000 0x400>;
687 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
688 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
689 clock-names = "mclk";
690 pinctrl-names = "default";
691 pinctrl-0 = <&dcmi_pins>;
692 dmas = <&dma2 1 1 0x414 0x3>;
698 compatible = "st,stm32-rng";
699 reg = <0x50060800 0x400>;
701 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
708 clocks = <&rcc 1 SYSTICK>;