2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved
3 * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include "skeleton.dtsi"
45 #include "armv7-m.dtsi"
46 #include <dt-bindings/clock/stm32fx-clock.h>
47 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
65 compatible = "fixed-clock";
66 clock-frequency = <32000>;
69 clk_i2s_ckin: i2s-ckin {
71 compatible = "fixed-clock";
72 clock-frequency = <0>;
77 timer2: timer@40000000 {
78 compatible = "st,stm32-timer";
79 reg = <0x40000000 0x400>;
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
85 timers2: timers@40000000 {
88 compatible = "st,stm32-timers";
89 reg = <0x40000000 0x400>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
95 compatible = "st,stm32-pwm";
100 compatible = "st,stm32-timer-trigger";
106 timer3: timer@40000400 {
107 compatible = "st,stm32-timer";
108 reg = <0x40000400 0x400>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
114 timers3: timers@40000400 {
115 #address-cells = <1>;
117 compatible = "st,stm32-timers";
118 reg = <0x40000400 0x400>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
124 compatible = "st,stm32-pwm";
129 compatible = "st,stm32-timer-trigger";
135 timer4: timer@40000800 {
136 compatible = "st,stm32-timer";
137 reg = <0x40000800 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
143 timers4: timers@40000800 {
144 #address-cells = <1>;
146 compatible = "st,stm32-timers";
147 reg = <0x40000800 0x400>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
153 compatible = "st,stm32-pwm";
158 compatible = "st,stm32-timer-trigger";
164 timer5: timer@40000c00 {
165 compatible = "st,stm32-timer";
166 reg = <0x40000c00 0x400>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
171 timers5: timers@40000c00 {
172 #address-cells = <1>;
174 compatible = "st,stm32-timers";
175 reg = <0x40000C00 0x400>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
181 compatible = "st,stm32-pwm";
186 compatible = "st,stm32-timer-trigger";
192 timer6: timer@40001000 {
193 compatible = "st,stm32-timer";
194 reg = <0x40001000 0x400>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
200 timers6: timers@40001000 {
201 #address-cells = <1>;
203 compatible = "st,stm32-timers";
204 reg = <0x40001000 0x400>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
210 compatible = "st,stm32-timer-trigger";
216 timer7: timer@40001400 {
217 compatible = "st,stm32-timer";
218 reg = <0x40001400 0x400>;
220 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
224 timers7: timers@40001400 {
225 #address-cells = <1>;
227 compatible = "st,stm32-timers";
228 reg = <0x40001400 0x400>;
229 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
234 compatible = "st,stm32-timer-trigger";
240 timers12: timers@40001800 {
241 #address-cells = <1>;
243 compatible = "st,stm32-timers";
244 reg = <0x40001800 0x400>;
245 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
250 compatible = "st,stm32-pwm";
255 compatible = "st,stm32-timer-trigger";
261 timers13: timers@40001c00 {
262 #address-cells = <1>;
264 compatible = "st,stm32-timers";
265 reg = <0x40001C00 0x400>;
266 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
271 compatible = "st,stm32-pwm";
276 timers14: timers@40002000 {
277 #address-cells = <1>;
279 compatible = "st,stm32-timers";
280 reg = <0x40002000 0x400>;
281 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
286 compatible = "st,stm32-pwm";
292 compatible = "st,stm32-rtc";
293 reg = <0x40002800 0x400>;
294 clocks = <&rcc 1 CLK_RTC>;
295 clock-names = "ck_rtc";
296 assigned-clocks = <&rcc 1 CLK_RTC>;
297 assigned-clock-parents = <&rcc 1 CLK_LSE>;
298 interrupt-parent = <&exti>;
300 interrupt-names = "alarm";
301 st,syscfg = <&pwrcfg>;
305 iwdg: watchdog@40003000 {
306 compatible = "st,stm32-iwdg";
307 reg = <0x40003000 0x400>;
312 usart2: serial@40004400 {
313 compatible = "st,stm32-uart";
314 reg = <0x40004400 0x400>;
316 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
320 usart3: serial@40004800 {
321 compatible = "st,stm32-uart";
322 reg = <0x40004800 0x400>;
324 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
326 dmas = <&dma1 1 4 0x400 0x0>,
327 <&dma1 3 4 0x400 0x0>;
328 dma-names = "rx", "tx";
331 usart4: serial@40004c00 {
332 compatible = "st,stm32-uart";
333 reg = <0x40004c00 0x400>;
335 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
339 usart5: serial@40005000 {
340 compatible = "st,stm32-uart";
341 reg = <0x40005000 0x400>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
348 compatible = "st,stm32f4-i2c";
349 reg = <0x40005400 0x400>;
352 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
354 #address-cells = <1>;
360 compatible = "st,stm32f4-dac-core";
361 reg = <0x40007400 0x400>;
362 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
363 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
364 clock-names = "pclk";
365 #address-cells = <1>;
370 compatible = "st,stm32-dac";
371 #io-channels-cells = <1>;
377 compatible = "st,stm32-dac";
378 #io-channels-cells = <1>;
384 usart7: serial@40007800 {
385 compatible = "st,stm32-uart";
386 reg = <0x40007800 0x400>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
392 usart8: serial@40007c00 {
393 compatible = "st,stm32-uart";
394 reg = <0x40007c00 0x400>;
396 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
400 timers1: timers@40010000 {
401 #address-cells = <1>;
403 compatible = "st,stm32-timers";
404 reg = <0x40010000 0x400>;
405 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
410 compatible = "st,stm32-pwm";
415 compatible = "st,stm32-timer-trigger";
421 timers8: timers@40010400 {
422 #address-cells = <1>;
424 compatible = "st,stm32-timers";
425 reg = <0x40010400 0x400>;
426 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
431 compatible = "st,stm32-pwm";
436 compatible = "st,stm32-timer-trigger";
442 usart1: serial@40011000 {
443 compatible = "st,stm32-uart";
444 reg = <0x40011000 0x400>;
446 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
448 dmas = <&dma2 2 4 0x400 0x0>,
449 <&dma2 7 4 0x400 0x0>;
450 dma-names = "rx", "tx";
453 usart6: serial@40011400 {
454 compatible = "st,stm32-uart";
455 reg = <0x40011400 0x400>;
457 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
462 compatible = "st,stm32f4-adc-core";
463 reg = <0x40012000 0x400>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
467 interrupt-controller;
468 #interrupt-cells = <1>;
469 #address-cells = <1>;
474 compatible = "st,stm32f4-adc";
475 #io-channel-cells = <1>;
477 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
478 interrupt-parent = <&adc>;
480 dmas = <&dma2 0 0 0x400 0x0>;
486 compatible = "st,stm32f4-adc";
487 #io-channel-cells = <1>;
489 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
490 interrupt-parent = <&adc>;
492 dmas = <&dma2 3 1 0x400 0x0>;
498 compatible = "st,stm32f4-adc";
499 #io-channel-cells = <1>;
501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
502 interrupt-parent = <&adc>;
504 dmas = <&dma2 1 2 0x400 0x0>;
510 syscfg: system-config@40013800 {
511 compatible = "syscon";
512 reg = <0x40013800 0x400>;
515 exti: interrupt-controller@40013c00 {
516 compatible = "st,stm32-exti";
517 interrupt-controller;
518 #interrupt-cells = <2>;
519 reg = <0x40013C00 0x400>;
520 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
523 timers9: timers@40014000 {
524 #address-cells = <1>;
526 compatible = "st,stm32-timers";
527 reg = <0x40014000 0x400>;
528 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
533 compatible = "st,stm32-pwm";
538 compatible = "st,stm32-timer-trigger";
544 timers10: timers@40014400 {
545 #address-cells = <1>;
547 compatible = "st,stm32-timers";
548 reg = <0x40014400 0x400>;
549 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
554 compatible = "st,stm32-pwm";
559 timers11: timers@40014800 {
560 #address-cells = <1>;
562 compatible = "st,stm32-timers";
563 reg = <0x40014800 0x400>;
564 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
569 compatible = "st,stm32-pwm";
574 pwrcfg: power-config@40007000 {
575 compatible = "syscon";
576 reg = <0x40007000 0x400>;
579 sdio: sdio@40012c00 {
580 compatible = "st,stm32f4xx-sdio";
581 reg = <0x40012c00 0x400>;
582 clocks = <&rcc 0 171>;
585 pinctrl-0 = <&sdio_pins>;
586 pinctrl-1 = <&sdio_pins_od>;
587 pinctrl-names = "default", "opendrain";
588 max-frequency = <48000000>;
591 ltdc: display-controller@40016800 {
592 compatible = "st,stm32-ltdc";
593 reg = <0x40016800 0x200>;
594 interrupts = <88>, <89>;
595 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
596 clocks = <&rcc 1 CLK_LCD>;
602 compatible = "st,stm32f4-crc";
603 reg = <0x40023000 0x400>;
604 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
611 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
612 reg = <0x40023800 0x400>;
613 clocks = <&clk_hse>, <&clk_i2s_ckin>;
614 st,syscfg = <&pwrcfg>;
615 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
616 assigned-clock-rates = <1000000>;
619 dma1: dma-controller@40026000 {
620 compatible = "st,stm32-dma";
621 reg = <0x40026000 0x400>;
630 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
634 dma2: dma-controller@40026400 {
635 compatible = "st,stm32-dma";
636 reg = <0x40026400 0x400>;
645 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
650 mac: ethernet@40028000 {
651 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
652 reg = <0x40028000 0x8000>;
653 reg-names = "stmmaceth";
655 interrupt-names = "macirq";
656 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
657 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
658 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
659 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
660 st,syscon = <&syscfg 0x4>;
666 usbotg_hs: usb@40040000 {
667 compatible = "snps,dwc2";
668 reg = <0x40040000 0x40000>;
670 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
675 usbotg_fs: usb@50000000 {
676 compatible = "st,stm32f4x9-fsotg";
677 reg = <0x50000000 0x40000>;
679 clocks = <&rcc 0 39>;
684 dcmi: dcmi@50050000 {
685 compatible = "st,stm32-dcmi";
686 reg = <0x50050000 0x400>;
688 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
689 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
690 clock-names = "mclk";
691 pinctrl-names = "default";
692 pinctrl-0 = <&dcmi_pins>;
693 dmas = <&dma2 1 1 0x414 0x3>;
699 compatible = "st,stm32-rng";
700 reg = <0x50060800 0x400>;
702 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
709 clocks = <&rcc 1 SYSTICK>;