1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
7 #include <dt-bindings/memory/stm32-sdram.h>
14 /* Aliases for gpios so as to use sequence */
35 compatible = "st,stm32-fmc";
36 reg = <0xA0000000 0x1000>;
37 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
38 pinctrl-0 = <&fmc_pins>;
39 pinctrl-names = "default";
43 * Memory configuration from sdram datasheet
47 st,sdram-control = /bits/ 8 <NO_COL_8
55 st,sdram-timing = /bits/ 8 <TMRD_3
61 st,sdram-refcount = < 1386 >;
88 compatible = "st,stm32-gpio";
93 compatible = "st,stm32-gpio";
98 compatible = "st,stm32-gpio";
103 compatible = "st,stm32-gpio";
108 compatible = "st,stm32-gpio";
113 compatible = "st,stm32-gpio";
118 compatible = "st,stm32-gpio";
123 compatible = "st,stm32-gpio";
128 compatible = "st,stm32-gpio";
133 compatible = "st,stm32-gpio";
138 compatible = "st,stm32-gpio";
143 usart1_pins_a: usart1@0 {
157 pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
158 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
159 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
160 <STM32_PINMUX('E',15, AF12)>, /* D12 */
161 <STM32_PINMUX('E',14, AF12)>, /* D11 */
162 <STM32_PINMUX('E',13, AF12)>, /* D10 */
163 <STM32_PINMUX('E',12, AF12)>, /* D09 */
164 <STM32_PINMUX('E',11, AF12)>, /* D08 */
165 <STM32_PINMUX('E',10, AF12)>, /* D07 */
166 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
167 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
168 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
169 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
170 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
171 <STM32_PINMUX('D',15, AF12)>, /* D01 */
172 <STM32_PINMUX('D',14, AF12)>, /* D00 */
174 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
175 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
177 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
178 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
180 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
181 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
182 <STM32_PINMUX('F',15, AF12)>, /* A09 */
183 <STM32_PINMUX('F',14, AF12)>, /* A08 */
184 <STM32_PINMUX('F',13, AF12)>, /* A07 */
185 <STM32_PINMUX('F',12, AF12)>, /* A06 */
186 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
187 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
188 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
189 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
190 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
191 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
193 <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
194 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
195 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
196 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
197 <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
198 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */