arch/arm/dts/stm32f4-pinctrl.dtsi

   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  45 #include <dt-bindings/mfd/stm32f4-rcc.h>
  46
  47 / {
  48         soc {
  49                 pinctrl: pin-controller {
  50                         #address-cells = <1>;
  51                         #size-cells = <1>;
  52                         ranges = <0 0x40020000 0x3000>;
  53                         interrupt-parent = <&exti>;
  54                         st,syscfg = <&syscfg 0x8>;
  55                         pins-are-numbered;
  56
  57                         gpioa: gpio@40020000 {
  58                                 gpio-controller;
  59                                 #gpio-cells = <2>;
  60                                 interrupt-controller;
  61                                 #interrupt-cells = <2>;
  62                                 reg = <0x0 0x400>;
  63                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
  64                                 st,bank-name = "GPIOA";
  65                         };
  66
  67                         gpiob: gpio@40020400 {
  68                                 gpio-controller;
  69                                 #gpio-cells = <2>;
  70                                 interrupt-controller;
  71                                 #interrupt-cells = <2>;
  72                                 reg = <0x400 0x400>;
  73                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
  74                                 st,bank-name = "GPIOB";
  75                         };
  76
  77                         gpioc: gpio@40020800 {
  78                                 gpio-controller;
  79                                 #gpio-cells = <2>;
  80                                 interrupt-controller;
  81                                 #interrupt-cells = <2>;
  82                                 reg = <0x800 0x400>;
  83                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
  84                                 st,bank-name = "GPIOC";
  85                         };
  86
  87                         gpiod: gpio@40020c00 {
  88                                 gpio-controller;
  89                                 #gpio-cells = <2>;
  90                                 interrupt-controller;
  91                                 #interrupt-cells = <2>;
  92                                 reg = <0xc00 0x400>;
  93                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
  94                                 st,bank-name = "GPIOD";
  95                         };
  96
  97                         gpioe: gpio@40021000 {
  98                                 gpio-controller;
  99                                 #gpio-cells = <2>;
 100                                 interrupt-controller;
 101                                 #interrupt-cells = <2>;
 102                                 reg = <0x1000 0x400>;
 103                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
 104                                 st,bank-name = "GPIOE";
 105                         };
 106
 107                         gpiof: gpio@40021400 {
 108                                 gpio-controller;
 109                                 #gpio-cells = <2>;
 110                                 interrupt-controller;
 111                                 #interrupt-cells = <2>;
 112                                 reg = <0x1400 0x400>;
 113                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
 114                                 st,bank-name = "GPIOF";
 115                         };
 116
 117                         gpiog: gpio@40021800 {
 118                                 gpio-controller;
 119                                 #gpio-cells = <2>;
 120                                 interrupt-controller;
 121                                 #interrupt-cells = <2>;
 122                                 reg = <0x1800 0x400>;
 123                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
 124                                 st,bank-name = "GPIOG";
 125                         };
 126
 127                         gpioh: gpio@40021c00 {
 128                                 gpio-controller;
 129                                 #gpio-cells = <2>;
 130                                 interrupt-controller;
 131                                 #interrupt-cells = <2>;
 132                                 reg = <0x1c00 0x400>;
 133                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
 134                                 st,bank-name = "GPIOH";
 135                         };
 136
 137                         gpioi: gpio@40022000 {
 138                                 gpio-controller;
 139                                 #gpio-cells = <2>;
 140                                 interrupt-controller;
 141                                 #interrupt-cells = <2>;
 142                                 reg = <0x2000 0x400>;
 143                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
 144                                 st,bank-name = "GPIOI";
 145                         };
 146
 147                         gpioj: gpio@40022400 {
 148                                 gpio-controller;
 149                                 #gpio-cells = <2>;
 150                                 interrupt-controller;
 151                                 #interrupt-cells = <2>;
 152                                 reg = <0x2400 0x400>;
 153                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
 154                                 st,bank-name = "GPIOJ";
 155                         };
 156
 157                         gpiok: gpio@40022800 {
 158                                 gpio-controller;
 159                                 #gpio-cells = <2>;
 160                                 interrupt-controller;
 161                                 #interrupt-cells = <2>;
 162                                 reg = <0x2800 0x400>;
 163                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
 164                                 st,bank-name = "GPIOK";
 165                         };
 166
 167                         usart1_pins_a: usart1@0 {
 168                                 pins1 {
 169                                         pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
 170                                         bias-disable;
 171                                         drive-push-pull;
 172                                         slew-rate = <0>;
 173                                 };
 174                                 pins2 {
 175                                         pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
 176                                         bias-disable;
 177                                 };
 178                         };
 179
 180                         usart3_pins_a: usart3@0 {
 181                                 pins1 {
 182                                         pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
 183                                         bias-disable;
 184                                         drive-push-pull;
 185                                         slew-rate = <0>;
 186                                 };
 187                                 pins2 {
 188                                         pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
 189                                         bias-disable;
 190                                 };
 191                         };
 192
 193                         usbotg_fs_pins_a: usbotg_fs@0 {
 194                                 pins {
 195                                         pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
 196                                                  <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
 197                                                  <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
 198                                         bias-disable;
 199                                         drive-push-pull;
 200                                         slew-rate = <2>;
 201                                 };
 202                         };
 203
 204                         usbotg_fs_pins_b: usbotg_fs@1 {
 205                                 pins {
 206                                         pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
 207                                                  <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
 208                                                  <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
 209                                         bias-disable;
 210                                         drive-push-pull;
 211                                         slew-rate = <2>;
 212                                 };
 213                         };
 214
 215                         usbotg_hs_pins_a: usbotg_hs@0 {
 216                                 pins {
 217                                         pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
 218                                                  <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
 219                                                  <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
 220                                                  <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
 221                                                  <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
 222                                                  <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
 223                                                  <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
 224                                                  <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
 225                                                  <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
 226                                                  <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
 227                                                  <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
 228                                                  <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
 229                                         bias-disable;
 230                                         drive-push-pull;
 231                                         slew-rate = <2>;
 232                                 };
 233                         };
 234
 235                         ethernet_mii: mii@0 {
 236                                 pins {
 237                                         pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
 238                                                  <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
 239                                                  <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
 240                                                  <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
 241                                                  <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
 242                                                  <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
 243                                                  <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
 244                                                  <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
 245                                                  <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
 246                                                  <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
 247                                                  <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
 248                                                  <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
 249                                                  <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
 250                                                  <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
 251                                         slew-rate = <2>;
 252                                 };
 253                         };
 254
 255                         adc3_in8_pin: adc@200 {
 256                                 pins {
 257                                         pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
 258                                 };
 259                         };
 260
 261                         pwm1_pins: pwm@1 {
 262                                 pins {
 263                                         pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
 264                                                  <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
 265                                                  <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
 266                                 };
 267                         };
 268
 269                         pwm3_pins: pwm@3 {
 270                                 pins {
 271                                         pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
 272                                                  <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
 273                                 };
 274                         };
 275
 276                         i2c1_pins: i2c1@0 {
 277                                 pins {
 278                                         pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
 279                                                  <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
 280                                         bias-disable;
 281                                         drive-open-drain;
 282                                         slew-rate = <3>;
 283                                 };
 284                         };
 285
 286                         ltdc_pins: ltdc@0 {
 287                                 pins {
 288                                         pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
 289                                                  <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
 290                                                  <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
 291                                                  <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
 292                                                  <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
 293                                                  <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
 294                                                  <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
 295                                                  <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
 296                                                  <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
 297                                                  <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
 298                                                  <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
 299                                                  <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
 300                                                  <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
 301                                                  <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
 302                                                  <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
 303                                                  <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
 304                                                  <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
 305                                                  <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
 306                                                  <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
 307                                                  <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
 308                                                  <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
 309                                                  <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
 310                                                  <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
 311                                                  <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
 312                                                  <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
 313                                                  <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
 314                                                  <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
 315                                                  <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
 316                                         slew-rate = <2>;
 317                                 };
 318                         };
 319
 320                         dcmi_pins: dcmi@0 {
 321                                 pins {
 322                                         pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
 323                                                  <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
 324                                                  <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
 325                                                  <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
 326                                                  <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
 327                                                  <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
 328                                                  <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
 329                                                  <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
 330                                                  <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
 331                                                  <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
 332                                                  <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
 333                                                  <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
 334                                                  <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
 335                                                  <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
 336                                                  <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
 337                                         bias-disable;
 338                                         drive-push-pull;
 339                                         slew-rate = <3>;
 340                                 };
 341                         };
 342
 343                         sdio_pins: sdio_pins@0 {
 344                                 pins {
 345                                         pinmux = <STM32_PINMUX('C', 8, AF12)>,
 346                                                  <STM32_PINMUX('C', 9, AF12)>,
 347                                                  <STM32_PINMUX('C', 10, AF12)>,
 348                                                  <STM32_PINMUX('c', 11, AF12)>,
 349                                                  <STM32_PINMUX('C', 12, AF12)>,
 350                                                  <STM32_PINMUX('D', 2, AF12)>;
 351                                         drive-push-pull;
 352                                         slew-rate = <2>;
 353                                 };
 354                         };
 355
 356                         sdio_pins_od: sdio_pins_od@0 {
 357                                 pins1 {
 358                                         pinmux = <STM32_PINMUX('C', 8, AF12)>,
 359                                                  <STM32_PINMUX('C', 9, AF12)>,
 360                                                  <STM32_PINMUX('C', 10, AF12)>,
 361                                                  <STM32_PINMUX('C', 11, AF12)>,
 362                                                  <STM32_PINMUX('C', 12, AF12)>;
 363                                         drive-push-pull;
 364                                         slew-rate = <2>;
 365                                 };
 366
 367                                 pins2 {
 368                                         pinmux = <STM32_PINMUX('D', 2, AF12)>;
 369                                         drive-open-drain;
 370                                         slew-rate = <2>;
 371                                 };
 372                         };
 373                 };
 374         };
 375 };