arm64: zynqmp: Use only earlycon bootargs instead of full one
[oweals/u-boot.git] / arch / arm / dts / stih410-clock.dtsi
1 /*
2  * Copyright (C) 2014 STMicroelectronics R&D Limited
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 #include <dt-bindings/clock/stih410-clks.h>
9 / {
10         clocks {
11                 #address-cells = <1>;
12                 #size-cells = <1>;
13                 ranges;
14
15                 compatible = "st,stih410-clk", "simple-bus";
16
17                 /*
18                  * Fixed 30MHz oscillator inputs to SoC
19                  */
20                 clk_sysin: clk-sysin {
21                         #clock-cells = <0>;
22                         compatible = "fixed-clock";
23                         clock-frequency = <30000000>;
24                         clock-output-names = "CLK_SYSIN";
25                 };
26
27                 /*
28                  * ARM Peripheral clock for timers
29                  */
30                 arm_periph_clk: clk-m-a9-periphs {
31                         #clock-cells = <0>;
32                         compatible = "fixed-factor-clock";
33                         clocks = <&clk_m_a9>;
34                         clock-div = <2>;
35                         clock-mult = <1>;
36                 };
37
38                 /*
39                  * A9 PLL.
40                  */
41                 clockgen-a9@92b0000 {
42                         compatible = "st,clkgen-c32";
43                         reg = <0x92b0000 0xffff>;
44
45                         clockgen_a9_pll: clockgen-a9-pll {
46                                 #clock-cells = <1>;
47                                 compatible = "st,stih407-clkgen-plla9";
48
49                                 clocks = <&clk_sysin>;
50
51                                 clock-output-names = "clockgen-a9-pll-odf";
52                         };
53                 };
54
55                 /*
56                  * ARM CPU related clocks.
57                  */
58                 clk_m_a9: clk-m-a9@92b0000 {
59                         #clock-cells = <0>;
60                         compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61                         reg = <0x92b0000 0x10000>;
62
63                         clocks = <&clockgen_a9_pll 0>,
64                                  <&clockgen_a9_pll 0>,
65                                  <&clk_s_c0_flexgen 13>,
66                                  <&clk_m_a9_ext2f_div2>;
67                 };
68
69                 /*
70                  * ARM Peripheral clock for timers
71                  */
72                 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73                         #clock-cells = <0>;
74                         compatible = "fixed-factor-clock";
75
76                         clocks = <&clk_s_c0_flexgen 13>;
77
78                         clock-output-names = "clk-m-a9-ext2f-div2";
79
80                         clock-div = <2>;
81                         clock-mult = <1>;
82                 };
83
84                 /*
85                  * Bootloader initialized system infrastructure clock for
86                  * serial devices.
87                  */
88                 clk_ext2f_a9: clockgen-c0@13 {
89                         #clock-cells = <0>;
90                         compatible = "fixed-clock";
91                         clock-frequency = <200000000>;
92                         clock-output-names = "clk-s-icn-reg-0";
93                 };
94
95                 clockgen-a@090ff000 {
96                         compatible = "st,clkgen-c32";
97                         reg = <0x90ff000 0x1000>;
98
99                         clk_s_a0_pll: clk-s-a0-pll {
100                                 #clock-cells = <1>;
101                                 compatible = "st,clkgen-pll0";
102
103                                 clocks = <&clk_sysin>;
104
105                                 clock-output-names = "clk-s-a0-pll-ofd-0";
106                                 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
107                         };
108
109                         clk_s_a0_flexgen: clk-s-a0-flexgen {
110                                 compatible = "st,flexgen";
111
112                                 #clock-cells = <1>;
113
114                                 clocks = <&clk_s_a0_pll 0>,
115                                          <&clk_sysin>;
116
117                                 clock-output-names = "clk-ic-lmi0",
118                                                      "clk-ic-lmi1";
119                                 clock-critical = <CLK_IC_LMI0>;
120                         };
121                 };
122
123                 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
124                         #clock-cells = <1>;
125                         compatible = "st,quadfs-pll";
126                         reg = <0x9103000 0x1000>;
127
128                         clocks = <&clk_sysin>;
129
130                         clock-output-names = "clk-s-c0-fs0-ch0",
131                                              "clk-s-c0-fs0-ch1",
132                                              "clk-s-c0-fs0-ch2",
133                                              "clk-s-c0-fs0-ch3";
134                         clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
135                 };
136
137                 clk_s_c0: clockgen-c@09103000 {
138                         compatible = "st,clkgen-c32";
139                         reg = <0x9103000 0x1000>;
140
141                         clk_s_c0_pll0: clk-s-c0-pll0 {
142                                 #clock-cells = <1>;
143                                 compatible = "st,clkgen-pll0";
144
145                                 clocks = <&clk_sysin>;
146
147                                 clock-output-names = "clk-s-c0-pll0-odf-0";
148                                 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
149                         };
150
151                         clk_s_c0_pll1: clk-s-c0-pll1 {
152                                 #clock-cells = <1>;
153                                 compatible = "st,clkgen-pll1";
154
155                                 clocks = <&clk_sysin>;
156
157                                 clock-output-names = "clk-s-c0-pll1-odf-0";
158                         };
159
160                         clk_s_c0_flexgen: clk-s-c0-flexgen {
161                                 #clock-cells = <1>;
162                                 compatible = "st,flexgen";
163
164                                 clocks = <&clk_s_c0_pll0 0>,
165                                          <&clk_s_c0_pll1 0>,
166                                          <&clk_s_c0_quadfs 0>,
167                                          <&clk_s_c0_quadfs 1>,
168                                          <&clk_s_c0_quadfs 2>,
169                                          <&clk_s_c0_quadfs 3>,
170                                          <&clk_sysin>;
171
172                                 clock-output-names = "clk-icn-gpu",
173                                                      "clk-fdma",
174                                                      "clk-nand",
175                                                      "clk-hva",
176                                                      "clk-proc-stfe",
177                                                      "clk-proc-tp",
178                                                      "clk-rx-icn-dmu",
179                                                      "clk-rx-icn-hva",
180                                                      "clk-icn-cpu",
181                                                      "clk-tx-icn-dmu",
182                                                      "clk-mmc-0",
183                                                      "clk-mmc-1",
184                                                      "clk-jpegdec",
185                                                      "clk-ext2fa9",
186                                                      "clk-ic-bdisp-0",
187                                                      "clk-ic-bdisp-1",
188                                                      "clk-pp-dmu",
189                                                      "clk-vid-dmu",
190                                                      "clk-dss-lpc",
191                                                      "clk-st231-aud-0",
192                                                      "clk-st231-gp-1",
193                                                      "clk-st231-dmu",
194                                                      "clk-icn-lmi",
195                                                      "clk-tx-icn-disp-1",
196                                                      "clk-icn-sbc",
197                                                      "clk-stfe-frc2",
198                                                      "clk-eth-phy",
199                                                      "clk-eth-ref-phyclk",
200                                                      "clk-flash-promip",
201                                                      "clk-main-disp",
202                                                      "clk-aux-disp",
203                                                      "clk-compo-dvp",
204                                                      "clk-tx-icn-hades",
205                                                      "clk-rx-icn-hades",
206                                                      "clk-icn-reg-16",
207                                                      "clk-pp-hades",
208                                                      "clk-clust-hades",
209                                                      "clk-hwpe-hades",
210                                                      "clk-fc-hades";
211                                 clock-critical = <CLK_ICN_CPU>,
212                                                  <CLK_TX_ICN_DMU>,
213                                                  <CLK_EXT2F_A9>,
214                                                  <CLK_ICN_LMI>,
215                                                  <CLK_ICN_SBC>;
216                         };
217                 };
218
219                 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
220                         #clock-cells = <1>;
221                         compatible = "st,quadfs";
222                         reg = <0x9104000 0x1000>;
223
224                         clocks = <&clk_sysin>;
225
226                         clock-output-names = "clk-s-d0-fs0-ch0",
227                                              "clk-s-d0-fs0-ch1",
228                                              "clk-s-d0-fs0-ch2",
229                                              "clk-s-d0-fs0-ch3";
230                 };
231
232                 clockgen-d0@09104000 {
233                         compatible = "st,clkgen-c32";
234                         reg = <0x9104000 0x1000>;
235
236                         clk_s_d0_flexgen: clk-s-d0-flexgen {
237                                 #clock-cells = <1>;
238                                 compatible = "st,flexgen-audio", "st,flexgen";
239
240                                 clocks = <&clk_s_d0_quadfs 0>,
241                                          <&clk_s_d0_quadfs 1>,
242                                          <&clk_s_d0_quadfs 2>,
243                                          <&clk_s_d0_quadfs 3>,
244                                          <&clk_sysin>;
245
246                                 clock-output-names = "clk-pcm-0",
247                                                      "clk-pcm-1",
248                                                      "clk-pcm-2",
249                                                      "clk-spdiff",
250                                                      "clk-pcmr10-master",
251                                                      "clk-usb2-phy";
252                         };
253                 };
254
255                 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
256                         #clock-cells = <1>;
257                         compatible = "st,quadfs";
258                         reg = <0x9106000 0x1000>;
259
260                         clocks = <&clk_sysin>;
261
262                         clock-output-names = "clk-s-d2-fs0-ch0",
263                                              "clk-s-d2-fs0-ch1",
264                                              "clk-s-d2-fs0-ch2",
265                                              "clk-s-d2-fs0-ch3";
266                 };
267
268                 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
269                         #clock-cells = <0>;
270                         compatible = "fixed-clock";
271                         clock-frequency = <0>;
272                 };
273
274                 clockgen-d2@x9106000 {
275                         compatible = "st,clkgen-c32";
276                         reg = <0x9106000 0x1000>;
277
278                         clk_s_d2_flexgen: clk-s-d2-flexgen {
279                                 #clock-cells = <1>;
280                                 compatible = "st,flexgen-video", "st,flexgen";
281
282                                 clocks = <&clk_s_d2_quadfs 0>,
283                                          <&clk_s_d2_quadfs 1>,
284                                          <&clk_s_d2_quadfs 2>,
285                                          <&clk_s_d2_quadfs 3>,
286                                          <&clk_sysin>,
287                                          <&clk_sysin>,
288                                          <&clk_tmdsout_hdmi>;
289
290                                 clock-output-names = "clk-pix-main-disp",
291                                                      "clk-pix-pip",
292                                                      "clk-pix-gdp1",
293                                                      "clk-pix-gdp2",
294                                                      "clk-pix-gdp3",
295                                                      "clk-pix-gdp4",
296                                                      "clk-pix-aux-disp",
297                                                      "clk-denc",
298                                                      "clk-pix-hddac",
299                                                      "clk-hddac",
300                                                      "clk-sddac",
301                                                      "clk-pix-dvo",
302                                                      "clk-dvo",
303                                                      "clk-pix-hdmi",
304                                                      "clk-tmds-hdmi",
305                                                      "clk-ref-hdmiphy";
306                                                      };
307                 };
308
309                 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
310                         #clock-cells = <1>;
311                         compatible = "st,quadfs";
312                         reg = <0x9107000 0x1000>;
313
314                         clocks = <&clk_sysin>;
315
316                         clock-output-names = "clk-s-d3-fs0-ch0",
317                                              "clk-s-d3-fs0-ch1",
318                                              "clk-s-d3-fs0-ch2",
319                                              "clk-s-d3-fs0-ch3";
320                 };
321
322                 clockgen-d3@9107000 {
323                         compatible = "st,clkgen-c32";
324                         reg = <0x9107000 0x1000>;
325
326                         clk_s_d3_flexgen: clk-s-d3-flexgen {
327                                 #clock-cells = <1>;
328                                 compatible = "st,flexgen";
329
330                                 clocks = <&clk_s_d3_quadfs 0>,
331                                          <&clk_s_d3_quadfs 1>,
332                                          <&clk_s_d3_quadfs 2>,
333                                          <&clk_s_d3_quadfs 3>,
334                                          <&clk_sysin>;
335
336                                 clock-output-names = "clk-stfe-frc1",
337                                                      "clk-tsout-0",
338                                                      "clk-tsout-1",
339                                                      "clk-mchi",
340                                                      "clk-vsens-compo",
341                                                      "clk-frc1-remote",
342                                                      "clk-lpc-0",
343                                                      "clk-lpc-1";
344                         };
345                 };
346         };
347 };