1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Intel Corporation
6 #include "socfpga_stratix10.dtsi"
9 model = "SoCFPGA Stratix 10 SoCDK";
17 stdout-path = "serial0:115200n8";
21 compatible = "gpio-leds";
24 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
29 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
34 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
39 device_type = "memory";
41 reg = <0 0x00000000 0 0x80000000>,
42 <1 0x80000000 0 0x80000000>;
56 max-frame-size = <3800>;
61 compatible = "snps,dwmac-mdio";
62 phy0: ethernet-phy@0 {
65 txd0-skew-ps = <0>; /* -420ps */
66 txd1-skew-ps = <0>; /* -420ps */
67 txd2-skew-ps = <0>; /* -420ps */
68 txd3-skew-ps = <0>; /* -420ps */
69 rxd0-skew-ps = <420>; /* 0ps */
70 rxd1-skew-ps = <420>; /* 0ps */
71 rxd2-skew-ps = <420>; /* 0ps */
72 rxd3-skew-ps = <420>; /* 0ps */
73 txen-skew-ps = <0>; /* -420ps */
74 txc-skew-ps = <1860>; /* 960ps */
75 rxdv-skew-ps = <420>; /* 0ps */
76 rxc-skew-ps = <1680>; /* 780ps */
99 compatible = "n25q00a";
101 spi-max-frequency = <50000000>;
104 cdns,page-size = <256>;
105 cdns,block-size = <16>;
106 cdns,read-delay = <1>;
107 cdns,tshsl-ns = <50>;
108 cdns,tsd2d-ns = <50>;
113 compatible = "fixed-partitions";
114 #address-cells = <1>;
117 qspi_boot: partition@0 {
118 label = "Boot and fpga data";
119 reg = <0x0 0x4000000>;
122 qspi_rootfs: partition@4000000 {
123 label = "Root Filesystem - JFFS2";
124 reg = <0x4000000 0x4000000>;