1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Intel Corporation
6 #include "socfpga_stratix10.dtsi"
9 model = "SoCFPGA Stratix 10 SoCDK";
16 stdout-path = "serial0:115200n8";
20 compatible = "gpio-leds";
23 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
28 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
33 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
38 device_type = "memory";
40 reg = <0 0x00000000 0 0x80000000>,
41 <1 0x80000000 0 0x80000000>;
55 max-frame-size = <3800>;
60 compatible = "snps,dwmac-mdio";
61 phy0: ethernet-phy@0 {
64 txd0-skew-ps = <0>; /* -420ps */
65 txd1-skew-ps = <0>; /* -420ps */
66 txd2-skew-ps = <0>; /* -420ps */
67 txd3-skew-ps = <0>; /* -420ps */
68 rxd0-skew-ps = <420>; /* 0ps */
69 rxd1-skew-ps = <420>; /* 0ps */
70 rxd2-skew-ps = <420>; /* 0ps */
71 rxd3-skew-ps = <420>; /* 0ps */
72 txen-skew-ps = <0>; /* -420ps */
73 txc-skew-ps = <1860>; /* 960ps */
74 rxdv-skew-ps = <420>; /* 0ps */
75 rxc-skew-ps = <1680>; /* 780ps */
94 compatible = "n25q00a";
96 spi-max-frequency = <50000000>;
99 cdns,page-size = <256>;
100 cdns,block-size = <16>;
101 cdns,read-delay = <1>;
102 cdns,tshsl-ns = <50>;
103 cdns,tsd2d-ns = <50>;
108 compatible = "fixed-partitions";
109 #address-cells = <1>;
112 qspi_boot: partition@0 {
113 label = "Boot and fpga data";
114 reg = <0x0 0x4000000>;
117 qspi_rootfs: partition@4000000 {
118 label = "Root Filesystem - JFFS2";
119 reg = <0x4000000 0x4000000>;