arch/arm/dts/socfpga_stratix10.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Intel Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         compatible = "altr,socfpga-stratix10";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu0: cpu@0 {
  20                         compatible = "arm,cortex-a53", "arm,armv8";
  21                         device_type = "cpu";
  22                         enable-method = "psci";
  23                         reg = <0x0>;
  24                 };
  25
  26                 cpu1: cpu@1 {
  27                         compatible = "arm,cortex-a53", "arm,armv8";
  28                         device_type = "cpu";
  29                         enable-method = "psci";
  30                         reg = <0x1>;
  31                 };
  32
  33                 cpu2: cpu@2 {
  34                         compatible = "arm,cortex-a53", "arm,armv8";
  35                         device_type = "cpu";
  36                         enable-method = "psci";
  37                         reg = <0x2>;
  38                 };
  39
  40                 cpu3: cpu@3 {
  41                         compatible = "arm,cortex-a53", "arm,armv8";
  42                         device_type = "cpu";
  43                         enable-method = "psci";
  44                         reg = <0x3>;
  45                 };
  46         };
  47
  48         pmu {
  49                 compatible = "arm,armv8-pmuv3";
  50                 interrupts = <0 120 8>,
  51                              <0 121 8>,
  52                              <0 122 8>,
  53                              <0 123 8>;
  54                 interrupt-affinity = <&cpu0>,
  55                                      <&cpu1>,
  56                                      <&cpu2>,
  57                                      <&cpu3>;
  58                 interrupt-parent = <&intc>;
  59         };
  60
  61         psci {
  62                 compatible = "arm,psci-0.2";
  63                 method = "smc";
  64         };
  65
  66         intc: intc@fffc1000 {
  67                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  68                 #interrupt-cells = <3>;
  69                 interrupt-controller;
  70                 reg = <0x0 0xfffc1000 0x0 0x1000>,
  71                       <0x0 0xfffc2000 0x0 0x2000>,
  72                       <0x0 0xfffc4000 0x0 0x2000>,
  73                       <0x0 0xfffc6000 0x0 0x2000>;
  74         };
  75
  76         soc {
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 compatible = "simple-bus";
  80                 device_type = "soc";
  81                 interrupt-parent = <&intc>;
  82                 ranges = <0 0 0 0xffffffff>;
  83                 u-boot,dm-pre-reloc;
  84
  85                 clkmgr@ffd1000 {
  86                         compatible = "altr,clk-mgr";
  87                         reg = <0xffd10000 0x1000>;
  88                 };
  89
  90                 gmac0: ethernet@ff800000 {
  91                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  92                         reg = <0xff800000 0x2000>;
  93                         interrupts = <0 90 4>;
  94                         interrupt-names = "macirq";
  95                         mac-address = [00 00 00 00 00 00];
  96                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
  97                         reset-names = "stmmaceth";
  98                         status = "disabled";
  99                 };
 100
 101                 gmac1: ethernet@ff802000 {
 102                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 103                         reg = <0xff802000 0x2000>;
 104                         interrupts = <0 91 4>;
 105                         interrupt-names = "macirq";
 106                         mac-address = [00 00 00 00 00 00];
 107                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 108                         reset-names = "stmmaceth";
 109                         status = "disabled";
 110                 };
 111
 112                 gmac2: ethernet@ff804000 {
 113                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
 114                         reg = <0xff804000 0x2000>;
 115                         interrupts = <0 92 4>;
 116                         interrupt-names = "macirq";
 117                         mac-address = [00 00 00 00 00 00];
 118                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 119                         reset-names = "stmmaceth";
 120                         status = "disabled";
 121                 };
 122
 123                 gpio0: gpio@ffc03200 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         compatible = "snps,dw-apb-gpio";
 127                         reg = <0xffc03200 0x100>;
 128                         resets = <&rst GPIO0_RESET>;
 129                         status = "disabled";
 130
 131                         porta: gpio-controller@0 {
 132                                 compatible = "snps,dw-apb-gpio-port";
 133                                 gpio-controller;
 134                                 #gpio-cells = <2>;
 135                                 snps,nr-gpios = <24>;
 136                                 reg = <0>;
 137                                 interrupt-controller;
 138                                 #interrupt-cells = <2>;
 139                                 interrupts = <0 110 4>;
 140                                 bank-name = "porta";
 141                         };
 142                 };
 143
 144                 gpio1: gpio@ffc03300 {
 145                         #address-cells = <1>;
 146                         #size-cells = <0>;
 147                         compatible = "snps,dw-apb-gpio";
 148                         reg = <0xffc03300 0x100>;
 149                         resets = <&rst GPIO1_RESET>;
 150                         status = "disabled";
 151
 152                         portb: gpio-controller@0 {
 153                                 compatible = "snps,dw-apb-gpio-port";
 154                                 gpio-controller;
 155                                 #gpio-cells = <2>;
 156                                 snps,nr-gpios = <24>;
 157                                 reg = <0>;
 158                                 interrupt-controller;
 159                                 #interrupt-cells = <2>;
 160                                 interrupts = <0 111 4>;
 161                                 bank-name = "portb";
 162                         };
 163                 };
 164
 165                 i2c0: i2c@ffc02800 {
 166                         #address-cells = <1>;
 167                         #size-cells = <0>;
 168                         compatible = "snps,designware-i2c";
 169                         reg = <0xffc02800 0x100>;
 170                         interrupts = <0 103 4>;
 171                         resets = <&rst I2C0_RESET>;
 172                         reset-names = "i2c";
 173                         status = "disabled";
 174                 };
 175
 176                 i2c1: i2c@ffc02900 {
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         compatible = "snps,designware-i2c";
 180                         reg = <0xffc02900 0x100>;
 181                         interrupts = <0 104 4>;
 182                         resets = <&rst I2C1_RESET>;
 183                         reset-names = "i2c";
 184                         status = "disabled";
 185                 };
 186
 187                 i2c2: i2c@ffc02a00 {
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         compatible = "snps,designware-i2c";
 191                         reg = <0xffc02a00 0x100>;
 192                         interrupts = <0 105 4>;
 193                         resets = <&rst I2C2_RESET>;
 194                         reset-names = "i2c";
 195                         status = "disabled";
 196                 };
 197
 198                 i2c3: i2c@ffc02b00 {
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         compatible = "snps,designware-i2c";
 202                         reg = <0xffc02b00 0x100>;
 203                         interrupts = <0 106 4>;
 204                         resets = <&rst I2C3_RESET>;
 205                         reset-names = "i2c";
 206                         status = "disabled";
 207                 };
 208
 209                 i2c4: i2c@ffc02c00 {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212                         compatible = "snps,designware-i2c";
 213                         reg = <0xffc02c00 0x100>;
 214                         interrupts = <0 107 4>;
 215                         resets = <&rst I2C4_RESET>;
 216                         reset-names = "i2c";
 217                         status = "disabled";
 218                 };
 219
 220                 mmc: dwmmc0@ff808000 {
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         compatible = "altr,socfpga-dw-mshc";
 224                         reg = <0xff808000 0x1000>;
 225                         interrupts = <0 96 4>;
 226                         fifo-depth = <0x400>;
 227                         resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
 228                         u-boot,dm-pre-reloc;
 229                         status = "disabled";
 230                 };
 231
 232                 ocram: sram@ffe00000 {
 233                         compatible = "mmio-sram";
 234                         reg = <0xffe00000 0x100000>;
 235                 };
 236
 237                 rst: rstmgr@ffd11000 {
 238                         #reset-cells = <1>;
 239                         compatible = "altr,rst-mgr";
 240                         reg = <0xffd11000 0x1000>;
 241                         altr,modrst-offset = <0x20>;
 242                         u-boot,dm-pre-reloc;
 243                 };
 244
 245                 spi0: spi@ffda4000 {
 246                         compatible = "snps,dw-apb-ssi";
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         reg = <0xffda4000 0x1000>;
 250                         interrupts = <0 99 4>;
 251                         resets = <&rst SPIM0_RESET>;
 252                         reg-io-width = <4>;
 253                         num-chipselect = <4>;
 254                         bus-num = <0>;
 255                         status = "disabled";
 256                 };
 257
 258                 spi1: spi@ffda5000 {
 259                         compatible = "snps,dw-apb-ssi";
 260                         #address-cells = <1>;
 261                         #size-cells = <0>;
 262                         reg = <0xffda5000 0x1000>;
 263                         interrupts = <0 100 4>;
 264                         resets = <&rst SPIM1_RESET>;
 265                         reg-io-width = <4>;
 266                         num-chipselect = <4>;
 267                         bus-num = <0>;
 268                         status = "disabled";
 269                 };
 270
 271                 sysmgr: sysmgr@ffd12000 {
 272                         compatible = "altr,sys-mgr", "syscon";
 273                         reg = <0xffd12000 0x1000>;
 274                 };
 275
 276                 /* Local timer */
 277                 timer {
 278                         compatible = "arm,armv8-timer";
 279                         interrupts = <1 13 0xf08>,
 280                                      <1 14 0xf08>,
 281                                      <1 11 0xf08>,
 282                                      <1 10 0xf08>;
 283                 };
 284
 285                 timer0: timer0@ffc03000 {
 286                         compatible = "snps,dw-apb-timer";
 287                         interrupts = <0 113 4>;
 288                         reg = <0xffc03000 0x100>;
 289                 };
 290
 291                 timer1: timer1@ffc03100 {
 292                         compatible = "snps,dw-apb-timer";
 293                         interrupts = <0 114 4>;
 294                         reg = <0xffc03100 0x100>;
 295                 };
 296
 297                 timer2: timer2@ffd00000 {
 298                         compatible = "snps,dw-apb-timer";
 299                         interrupts = <0 115 4>;
 300                         reg = <0xffd00000 0x100>;
 301                 };
 302
 303                 timer3: timer3@ffd00100 {
 304                         compatible = "snps,dw-apb-timer";
 305                         interrupts = <0 116 4>;
 306                         reg = <0xffd00100 0x100>;
 307                 };
 308
 309                 uart0: serial0@ffc02000 {
 310                         compatible = "snps,dw-apb-uart";
 311                         reg = <0xffc02000 0x100>;
 312                         interrupts = <0 108 4>;
 313                         reg-shift = <2>;
 314                         reg-io-width = <4>;
 315                         resets = <&rst UART0_RESET>;
 316                         clock-frequency = <100000000>;
 317                         u-boot,dm-pre-reloc;
 318                         status = "disabled";
 319                 };
 320
 321                 uart1: serial1@ffc02100 {
 322                         compatible = "snps,dw-apb-uart";
 323                         reg = <0xffc02100 0x100>;
 324                         interrupts = <0 109 4>;
 325                         reg-shift = <2>;
 326                         reg-io-width = <4>;
 327                         resets = <&rst UART1_RESET>;
 328                         status = "disabled";
 329                 };
 330
 331                 usbphy0: usbphy@0 {
 332                         #phy-cells = <0>;
 333                         compatible = "usb-nop-xceiv";
 334                         status = "okay";
 335                 };
 336
 337                 usb0: usb@ffb00000 {
 338                         compatible = "snps,dwc2";
 339                         reg = <0xffb00000 0x40000>;
 340                         interrupts = <0 93 4>;
 341                         phys = <&usbphy0>;
 342                         phy-names = "usb2-phy";
 343                         resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
 344                         reset-names = "dwc2", "dwc2-ecc";
 345                         status = "disabled";
 346                 };
 347
 348                 usb1: usb@ffb40000 {
 349                         compatible = "snps,dwc2";
 350                         reg = <0xffb40000 0x40000>;
 351                         interrupts = <0 94 4>;
 352                         phys = <&usbphy0>;
 353                         phy-names = "usb2-phy";
 354                         resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
 355                         reset-names = "dwc2", "dwc2-ecc";
 356                         status = "disabled";
 357                 };
 358
 359                 watchdog0: watchdog@ffd00200 {
 360                         compatible = "snps,dw-wdt";
 361                         reg = <0xffd00200 0x100>;
 362                         interrupts = <0 117 4>;
 363                         resets = <&rst WATCHDOG0_RESET>;
 364                         u-boot,dm-pre-reloc;
 365                         status = "disabled";
 366                 };
 367
 368                 watchdog1: watchdog@ffd00300 {
 369                         compatible = "snps,dw-wdt";
 370                         reg = <0xffd00300 0x100>;
 371                         interrupts = <0 118 4>;
 372                         resets = <&rst WATCHDOG1_RESET>;
 373                         status = "disabled";
 374                 };
 375
 376                 watchdog2: watchdog@ffd00400 {
 377                         compatible = "snps,dw-wdt";
 378                         reg = <0xffd00400 0x100>;
 379                         interrupts = <0 125 4>;
 380                         resets = <&rst WATCHDOG2_RESET>;
 381                         status = "disabled";
 382                 };
 383
 384                 watchdog3: watchdog@ffd00500 {
 385                         compatible = "snps,dw-wdt";
 386                         reg = <0xffd00500 0x100>;
 387                         interrupts = <0 126 4>;
 388                         resets = <&rst WATCHDOG3_RESET>;
 389                         status = "disabled";
 390                 };
 391         };
 392 };