1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Intel Corporation
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "altr,socfpga-stratix10";
20 compatible = "arm,cortex-a53", "arm,armv8";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
49 compatible = "arm,armv8-pmuv3";
50 interrupts = <0 120 8>,
54 interrupt-affinity = <&cpu0>,
58 interrupt-parent = <&intc>;
62 compatible = "arm,psci-0.2";
67 compatible = "arm,gic-400", "arm,cortex-a15-gic";
68 #interrupt-cells = <3>;
70 reg = <0x0 0xfffc1000 0x0 0x1000>,
71 <0x0 0xfffc2000 0x0 0x2000>,
72 <0x0 0xfffc4000 0x0 0x2000>,
73 <0x0 0xfffc6000 0x0 0x2000>;
79 compatible = "simple-bus";
81 interrupt-parent = <&intc>;
82 ranges = <0 0 0 0xffffffff>;
86 compatible = "altr,clk-mgr";
87 reg = <0xffd10000 0x1000>;
90 gmac0: ethernet@ff800000 {
91 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
92 reg = <0xff800000 0x2000>;
93 interrupts = <0 90 4>;
94 interrupt-names = "macirq";
95 mac-address = [00 00 00 00 00 00];
96 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
97 reset-names = "stmmaceth";
98 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
102 gmac1: ethernet@ff802000 {
103 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
104 reg = <0xff802000 0x2000>;
105 interrupts = <0 91 4>;
106 interrupt-names = "macirq";
107 mac-address = [00 00 00 00 00 00];
108 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
109 reset-names = "stmmaceth";
110 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
114 gmac2: ethernet@ff804000 {
115 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
116 reg = <0xff804000 0x2000>;
117 interrupts = <0 92 4>;
118 interrupt-names = "macirq";
119 mac-address = [00 00 00 00 00 00];
120 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
121 reset-names = "stmmaceth";
122 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
126 gpio0: gpio@ffc03200 {
127 #address-cells = <1>;
129 compatible = "snps,dw-apb-gpio";
130 reg = <0xffc03200 0x100>;
131 resets = <&rst GPIO0_RESET>;
134 porta: gpio-controller@0 {
135 compatible = "snps,dw-apb-gpio-port";
138 snps,nr-gpios = <24>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 interrupts = <0 110 4>;
147 gpio1: gpio@ffc03300 {
148 #address-cells = <1>;
150 compatible = "snps,dw-apb-gpio";
151 reg = <0xffc03300 0x100>;
152 resets = <&rst GPIO1_RESET>;
155 portb: gpio-controller@0 {
156 compatible = "snps,dw-apb-gpio-port";
159 snps,nr-gpios = <24>;
161 interrupt-controller;
162 #interrupt-cells = <2>;
163 interrupts = <0 111 4>;
169 #address-cells = <1>;
171 compatible = "snps,designware-i2c";
172 reg = <0xffc02800 0x100>;
173 interrupts = <0 103 4>;
174 resets = <&rst I2C0_RESET>;
180 #address-cells = <1>;
182 compatible = "snps,designware-i2c";
183 reg = <0xffc02900 0x100>;
184 interrupts = <0 104 4>;
185 resets = <&rst I2C1_RESET>;
191 #address-cells = <1>;
193 compatible = "snps,designware-i2c";
194 reg = <0xffc02a00 0x100>;
195 interrupts = <0 105 4>;
196 resets = <&rst I2C2_RESET>;
202 #address-cells = <1>;
204 compatible = "snps,designware-i2c";
205 reg = <0xffc02b00 0x100>;
206 interrupts = <0 106 4>;
207 resets = <&rst I2C3_RESET>;
213 #address-cells = <1>;
215 compatible = "snps,designware-i2c";
216 reg = <0xffc02c00 0x100>;
217 interrupts = <0 107 4>;
218 resets = <&rst I2C4_RESET>;
223 mmc: dwmmc0@ff808000 {
224 #address-cells = <1>;
226 compatible = "altr,socfpga-dw-mshc";
227 reg = <0xff808000 0x1000>;
228 interrupts = <0 96 4>;
229 fifo-depth = <0x400>;
230 resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
235 ocram: sram@ffe00000 {
236 compatible = "mmio-sram";
237 reg = <0xffe00000 0x100000>;
241 compatible = "cdns,qspi-nor";
242 #address-cells = <1>;
244 reg = <0xff8d2000 0x100>,
245 <0xff900000 0x100000>;
246 interrupts = <0 3 4>;
247 cdns,fifo-depth = <128>;
248 cdns,fifo-width = <4>;
249 cdns,trigger-address = <0x00000000>;
253 rst: rstmgr@ffd11000 {
255 compatible = "altr,rst-mgr";
256 reg = <0xffd11000 0x1000>;
257 altr,modrst-offset = <0x20>;
262 compatible = "altr,sdr-ctl-s10";
263 reg = <0xf8000400 0x80>,
266 resets = <&rst DDRSCH_RESET>;
271 compatible = "snps,dw-apb-ssi";
272 #address-cells = <1>;
274 reg = <0xffda4000 0x1000>;
275 interrupts = <0 99 4>;
276 resets = <&rst SPIM0_RESET>;
278 num-chipselect = <4>;
284 compatible = "snps,dw-apb-ssi";
285 #address-cells = <1>;
287 reg = <0xffda5000 0x1000>;
288 interrupts = <0 100 4>;
289 resets = <&rst SPIM1_RESET>;
291 num-chipselect = <4>;
296 sysmgr: sysmgr@ffd12000 {
297 compatible = "altr,sys-mgr", "syscon";
298 reg = <0xffd12000 0x1000>;
303 compatible = "arm,armv8-timer";
304 interrupts = <1 13 0xf08>,
310 timer0: timer0@ffc03000 {
311 compatible = "snps,dw-apb-timer";
312 interrupts = <0 113 4>;
313 reg = <0xffc03000 0x100>;
316 timer1: timer1@ffc03100 {
317 compatible = "snps,dw-apb-timer";
318 interrupts = <0 114 4>;
319 reg = <0xffc03100 0x100>;
322 timer2: timer2@ffd00000 {
323 compatible = "snps,dw-apb-timer";
324 interrupts = <0 115 4>;
325 reg = <0xffd00000 0x100>;
328 timer3: timer3@ffd00100 {
329 compatible = "snps,dw-apb-timer";
330 interrupts = <0 116 4>;
331 reg = <0xffd00100 0x100>;
334 uart0: serial0@ffc02000 {
335 compatible = "snps,dw-apb-uart";
336 reg = <0xffc02000 0x100>;
337 interrupts = <0 108 4>;
340 resets = <&rst UART0_RESET>;
341 clock-frequency = <100000000>;
346 uart1: serial1@ffc02100 {
347 compatible = "snps,dw-apb-uart";
348 reg = <0xffc02100 0x100>;
349 interrupts = <0 109 4>;
352 resets = <&rst UART1_RESET>;
358 compatible = "usb-nop-xceiv";
363 compatible = "snps,dwc2";
364 reg = <0xffb00000 0x40000>;
365 interrupts = <0 93 4>;
367 phy-names = "usb2-phy";
368 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
369 reset-names = "dwc2", "dwc2-ecc";
374 compatible = "snps,dwc2";
375 reg = <0xffb40000 0x40000>;
376 interrupts = <0 94 4>;
378 phy-names = "usb2-phy";
379 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
380 reset-names = "dwc2", "dwc2-ecc";
384 watchdog0: watchdog@ffd00200 {
385 compatible = "snps,dw-wdt";
386 reg = <0xffd00200 0x100>;
387 interrupts = <0 117 4>;
388 resets = <&rst WATCHDOG0_RESET>;
393 watchdog1: watchdog@ffd00300 {
394 compatible = "snps,dw-wdt";
395 reg = <0xffd00300 0x100>;
396 interrupts = <0 118 4>;
397 resets = <&rst WATCHDOG1_RESET>;
401 watchdog2: watchdog@ffd00400 {
402 compatible = "snps,dw-wdt";
403 reg = <0xffd00400 0x100>;
404 interrupts = <0 125 4>;
405 resets = <&rst WATCHDOG2_RESET>;
409 watchdog3: watchdog@ffd00500 {
410 compatible = "snps,dw-wdt";
411 reg = <0xffd00500 0x100>;
412 interrupts = <0 126 4>;
413 resets = <&rst WATCHDOG3_RESET>;