arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
   2 /*
   3  * U-Boot additions
   4  *
   5  * Copyright (C) 2015 Marek Vasut <marex@denx.de>
   6  * Copyright (c) 2018 Simon Goldschmidt
   7  */
   8
   9 #include "socfpga-common-u-boot.dtsi"
  10
  11 /{
  12         aliases {
  13                 spi0 = "/soc/spi@ff705000";
  14                 udc0 = &usb0;
  15         };
  16 };
  17
  18 &watchdog0 {
  19         status = "disabled";
  20 };
  21
  22 &mmc {
  23         status = "disabled";
  24 };
  25
  26 &qspi {
  27         u-boot,dm-pre-reloc;
  28
  29         n25q128@0 {
  30                 compatible = "n25q128", "jedec,spi-nor";
  31                 u-boot,dm-pre-reloc;
  32         };
  33         n25q00@1 {
  34                 compatible = "n25q00", "jedec,spi-nor";
  35                 u-boot,dm-pre-reloc;
  36         };
  37 };
  38
  39 &uart0 {
  40         clock-frequency = <100000000>;
  41         u-boot,dm-pre-reloc;
  42 };
  43
  44 &uart1 {
  45         clock-frequency = <100000000>;
  46 };
  47
  48 &porta {
  49         bank-name = "porta";
  50 };
  51
  52 &portb {
  53         bank-name = "portb";
  54 };
  55
  56 &portc {
  57         bank-name = "portc";
  58 };
  59
  60 &watchdog0 {
  61         u-boot,dm-pre-reloc;
  62 };