arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  *
   5  *<auto-generated>
   6  *      This code was generated by a tool based on
   7  *      handoffs from both Qsys and Quartus.
   8  *
   9  *      Changes to this file may be lost if
  10  *      the code is regenerated.
  11  *</auto-generated>
  12  */
  13
  14 #include "socfpga_arria10.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19         model = "SOCFPGA Arria10 Dev Kit";      /* Bootloader setting: uboot.model */
  20
  21         chosen {
  22                 cff-file = "socfpga.rbf";       /* Bootloader setting: uboot.rbf_filename */
  23         };
  24
  25         /* Clock sources */
  26         clocks {
  27                 u-boot,dm-pre-reloc;
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 /* Clock source: altera_arria10_hps_eosc1 */
  32                 altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
  33                         u-boot,dm-pre-reloc;
  34                         compatible = "fixed-clock";
  35                         #clock-cells = <0>;
  36                         clock-frequency = <25000000>;
  37                         clock-output-names = "altera_arria10_hps_eosc1-clk";
  38                 };
  39
  40                 /* Clock source: altera_arria10_hps_cb_intosc_ls */
  41                 altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
  42                         u-boot,dm-pre-reloc;
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <60000000>;
  46                         clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
  47                 };
  48
  49                 /* Clock source: altera_arria10_hps_f2h_free */
  50                 altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
  51                         u-boot,dm-pre-reloc;
  52                         compatible = "fixed-clock";
  53                         #clock-cells = <0>;
  54                         clock-frequency = <200000000>;
  55                         clock-output-names = "altera_arria10_hps_f2h_free-clk";
  56                 };
  57         };
  58
  59         /*
  60          * Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
  61          * Version: 1.0
  62          * Binding: device
  63          */
  64         i_clk_mgr: clock_manager@0xffd04000 {
  65                 u-boot,dm-pre-reloc;
  66                 compatible = "altr,socfpga-a10-clk-init";
  67                 reg = <0xffd04000 0x00000200>;
  68                 reg-names = "soc_clock_manager_OCP_SLV";
  69
  70                 /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
  71                 mainpll {
  72                         u-boot,dm-pre-reloc;
  73                         vco0-psrc = <0>;        /* Field: vco0.psrc */
  74                         vco1-denom = <1>;       /* Field: vco1.denom */
  75                         vco1-numer = <191>;     /* Field: vco1.numer */
  76                         mpuclk-cnt = <0>;       /* Field: mpuclk.cnt */
  77                         mpuclk-src = <0>;       /* Field: mpuclk.src */
  78                         nocclk-cnt = <0>;       /* Field: nocclk.cnt */
  79                         nocclk-src = <0>;       /* Field: nocclk.src */
  80                         cntr2clk-cnt = <900>;   /* Field: cntr2clk.cnt */
  81                         cntr3clk-cnt = <900>;   /* Field: cntr3clk.cnt */
  82                         cntr4clk-cnt = <900>;   /* Field: cntr4clk.cnt */
  83                         cntr5clk-cnt = <900>;   /* Field: cntr5clk.cnt */
  84                         cntr6clk-cnt = <900>;   /* Field: cntr6clk.cnt */
  85                         cntr7clk-cnt = <900>;   /* Field: cntr7clk.cnt */
  86                         cntr7clk-src = <0>;     /* Field: cntr7clk.src */
  87                         cntr8clk-cnt = <900>;   /* Field: cntr8clk.cnt */
  88                         cntr9clk-cnt = <900>;   /* Field: cntr9clk.cnt */
  89                         cntr9clk-src = <0>;     /* Field: cntr9clk.src */
  90                         cntr15clk-cnt = <900>;  /* Field: cntr15clk.cnt */
  91                         nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
  92                         nocdiv-l4mpclk = <0>;   /* Field: nocdiv.l4mpclk */
  93                         nocdiv-l4spclk = <2>;   /* Field: nocdiv.l4spclk */
  94                         nocdiv-csatclk = <0>;   /* Field: nocdiv.csatclk */
  95                         nocdiv-cstraceclk = <1>;        /* Field: nocdiv.cstraceclk */
  96                         nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
  97                 };
  98
  99                 /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
 100                 perpll {
 101                         u-boot,dm-pre-reloc;
 102                         vco0-psrc = <0>;        /* Field: vco0.psrc */
 103                         vco1-denom = <1>;       /* Field: vco1.denom */
 104                         vco1-numer = <159>;     /* Field: vco1.numer */
 105                         cntr2clk-cnt = <7>;     /* Field: cntr2clk.cnt */
 106                         cntr2clk-src = <1>;     /* Field: cntr2clk.src */
 107                         cntr3clk-cnt = <900>;   /* Field: cntr3clk.cnt */
 108                         cntr3clk-src = <1>;     /* Field: cntr3clk.src */
 109                         cntr4clk-cnt = <19>;    /* Field: cntr4clk.cnt */
 110                         cntr4clk-src = <1>;     /* Field: cntr4clk.src */
 111                         cntr5clk-cnt = <499>;   /* Field: cntr5clk.cnt */
 112                         cntr5clk-src = <1>;     /* Field: cntr5clk.src */
 113                         cntr6clk-cnt = <9>;     /* Field: cntr6clk.cnt */
 114                         cntr6clk-src = <1>;     /* Field: cntr6clk.src */
 115                         cntr7clk-cnt = <900>;   /* Field: cntr7clk.cnt */
 116                         cntr8clk-cnt = <900>;   /* Field: cntr8clk.cnt */
 117                         cntr8clk-src = <0>;     /* Field: cntr8clk.src */
 118                         cntr9clk-cnt = <900>;   /* Field: cntr9clk.cnt */
 119                         emacctl-emac0sel = <0>; /* Field: emacctl.emac0sel */
 120                         emacctl-emac1sel = <0>; /* Field: emacctl.emac1sel */
 121                         emacctl-emac2sel = <0>; /* Field: emacctl.emac2sel */
 122                         gpiodiv-gpiodbclk = <32000>;    /* Field: gpiodiv.gpiodbclk */
 123                 };
 124
 125                 /* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
 126                 alteragrp {
 127                         u-boot,dm-pre-reloc;
 128                         nocclk = <0x0384000b>;  /* Register: nocclk */
 129                         mpuclk = <0x03840001>;  /* Register: mpuclk */
 130                 };
 131         };
 132
 133         /*
 134          * Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
 135          * Version: 1.0
 136          * Binding: pinmux
 137          */
 138         i_io48_pin_mux: pinmux@0xffd07000 {
 139                 u-boot,dm-pre-reloc;
 140                 #address-cells = <1>;
 141                 #size-cells = <1>;
 142                 compatible = "pinctrl-single";
 143                 reg = <0xffd07000 0x00000800>;
 144                 reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
 145
 146                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
 147                 shared {
 148                         u-boot,dm-pre-reloc;
 149                         reg = <0xffd07000 0x00000200>;
 150                         pinctrl-single,register-width = <32>;
 151                         pinctrl-single,function-mask = <0x0000000f>;
 152                         pinctrl-single,pins =
 153                                 <0x00000000 0x00000008>,        /* Register: pinmux_shared_io_q1_1 */
 154                                 <0x00000004 0x00000008>,        /* Register: pinmux_shared_io_q1_2 */
 155                                 <0x00000008 0x00000008>,        /* Register: pinmux_shared_io_q1_3 */
 156                                 <0x0000000c 0x00000008>,        /* Register: pinmux_shared_io_q1_4 */
 157                                 <0x00000010 0x00000008>,        /* Register: pinmux_shared_io_q1_5 */
 158                                 <0x00000014 0x00000008>,        /* Register: pinmux_shared_io_q1_6 */
 159                                 <0x00000018 0x00000008>,        /* Register: pinmux_shared_io_q1_7 */
 160                                 <0x0000001c 0x00000008>,        /* Register: pinmux_shared_io_q1_8 */
 161                                 <0x00000020 0x00000008>,        /* Register: pinmux_shared_io_q1_9 */
 162                                 <0x00000024 0x00000008>,        /* Register: pinmux_shared_io_q1_10 */
 163                                 <0x00000028 0x00000008>,        /* Register: pinmux_shared_io_q1_11 */
 164                                 <0x0000002c 0x00000008>,        /* Register: pinmux_shared_io_q1_12 */
 165                                 <0x00000030 0x00000004>,        /* Register: pinmux_shared_io_q2_1 */
 166                                 <0x00000034 0x00000004>,        /* Register: pinmux_shared_io_q2_2 */
 167                                 <0x00000038 0x00000004>,        /* Register: pinmux_shared_io_q2_3 */
 168                                 <0x0000003c 0x00000004>,        /* Register: pinmux_shared_io_q2_4 */
 169                                 <0x00000040 0x00000004>,        /* Register: pinmux_shared_io_q2_5 */
 170                                 <0x00000044 0x00000004>,        /* Register: pinmux_shared_io_q2_6 */
 171                                 <0x00000048 0x00000004>,        /* Register: pinmux_shared_io_q2_7 */
 172                                 <0x0000004c 0x00000004>,        /* Register: pinmux_shared_io_q2_8 */
 173                                 <0x00000050 0x00000004>,        /* Register: pinmux_shared_io_q2_9 */
 174                                 <0x00000054 0x00000004>,        /* Register: pinmux_shared_io_q2_10 */
 175                                 <0x00000058 0x00000004>,        /* Register: pinmux_shared_io_q2_11 */
 176                                 <0x0000005c 0x00000004>,        /* Register: pinmux_shared_io_q2_12 */
 177                                 <0x00000060 0x00000003>,        /* Register: pinmux_shared_io_q3_1 */
 178                                 <0x00000064 0x00000003>,        /* Register: pinmux_shared_io_q3_2 */
 179                                 <0x00000068 0x00000003>,        /* Register: pinmux_shared_io_q3_3 */
 180                                 <0x0000006c 0x00000003>,        /* Register: pinmux_shared_io_q3_4 */
 181                                 <0x00000070 0x00000003>,        /* Register: pinmux_shared_io_q3_5 */
 182                                 <0x00000074 0x0000000f>,        /* Register: pinmux_shared_io_q3_6 */
 183                                 <0x00000078 0x0000000a>,        /* Register: pinmux_shared_io_q3_7 */
 184                                 <0x0000007c 0x0000000a>,        /* Register: pinmux_shared_io_q3_8 */
 185                                 <0x00000080 0x0000000a>,        /* Register: pinmux_shared_io_q3_9 */
 186                                 <0x00000084 0x0000000a>,        /* Register: pinmux_shared_io_q3_10 */
 187                                 <0x00000088 0x00000001>,        /* Register: pinmux_shared_io_q3_11 */
 188                                 <0x0000008c 0x00000001>,        /* Register: pinmux_shared_io_q3_12 */
 189                                 <0x00000090 0x00000000>,        /* Register: pinmux_shared_io_q4_1 */
 190                                 <0x00000094 0x00000000>,        /* Register: pinmux_shared_io_q4_2 */
 191                                 <0x00000098 0x0000000f>,        /* Register: pinmux_shared_io_q4_3 */
 192                                 <0x0000009c 0x0000000c>,        /* Register: pinmux_shared_io_q4_4 */
 193                                 <0x000000a0 0x0000000f>,        /* Register: pinmux_shared_io_q4_5 */
 194                                 <0x000000a4 0x0000000f>,        /* Register: pinmux_shared_io_q4_6 */
 195                                 <0x000000a8 0x0000000a>,        /* Register: pinmux_shared_io_q4_7 */
 196                                 <0x000000ac 0x0000000a>,        /* Register: pinmux_shared_io_q4_8 */
 197                                 <0x000000b0 0x0000000c>,        /* Register: pinmux_shared_io_q4_9 */
 198                                 <0x000000b4 0x0000000c>,        /* Register: pinmux_shared_io_q4_10 */
 199                                 <0x000000b8 0x0000000c>,        /* Register: pinmux_shared_io_q4_11 */
 200                                 <0x000000bc 0x0000000c>;        /* Register: pinmux_shared_io_q4_12 */
 201                 };
 202
 203                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
 204                 dedicated {
 205                         u-boot,dm-pre-reloc;
 206                         reg = <0xffd07200 0x00000200>;
 207                         pinctrl-single,register-width = <32>;
 208                         pinctrl-single,function-mask = <0x0000000f>;
 209                         pinctrl-single,pins =
 210                                 <0x0000000c 0x00000008>,        /* Register: pinmux_dedicated_io_4 */
 211                                 <0x00000010 0x00000008>,        /* Register: pinmux_dedicated_io_5 */
 212                                 <0x00000014 0x00000008>,        /* Register: pinmux_dedicated_io_6 */
 213                                 <0x00000018 0x00000008>,        /* Register: pinmux_dedicated_io_7 */
 214                                 <0x0000001c 0x00000008>,        /* Register: pinmux_dedicated_io_8 */
 215                                 <0x00000020 0x00000008>,        /* Register: pinmux_dedicated_io_9 */
 216                                 <0x00000024 0x0000000a>,        /* Register: pinmux_dedicated_io_10 */
 217                                 <0x00000028 0x0000000a>,        /* Register: pinmux_dedicated_io_11 */
 218                                 <0x0000002c 0x00000008>,        /* Register: pinmux_dedicated_io_12 */
 219                                 <0x00000030 0x00000008>,        /* Register: pinmux_dedicated_io_13 */
 220                                 <0x00000034 0x00000008>,        /* Register: pinmux_dedicated_io_14 */
 221                                 <0x00000038 0x00000008>,        /* Register: pinmux_dedicated_io_15 */
 222                                 <0x0000003c 0x0000000d>,        /* Register: pinmux_dedicated_io_16 */
 223                                 <0x00000040 0x0000000d>;        /* Register: pinmux_dedicated_io_17 */
 224                 };
 225
 226                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
 227                 dedicated_cfg {
 228                         u-boot,dm-pre-reloc;
 229                         reg = <0xffd07200 0x00000200>;
 230                         pinctrl-single,register-width = <32>;
 231                         pinctrl-single,function-mask = <0x003f3f3f>;
 232                         pinctrl-single,pins =
 233                                 <0x00000100 0x00000101>,        /* Register: configuration_dedicated_io_bank */
 234                                 <0x00000104 0x000b080a>,        /* Register: configuration_dedicated_io_1 */
 235                                 <0x00000108 0x000b080a>,        /* Register: configuration_dedicated_io_2 */
 236                                 <0x0000010c 0x000b080a>,        /* Register: configuration_dedicated_io_3 */
 237                                 <0x00000110 0x000a282a>,        /* Register: configuration_dedicated_io_4 */
 238                                 <0x00000114 0x000a282a>,        /* Register: configuration_dedicated_io_5 */
 239                                 <0x00000118 0x0008282a>,        /* Register: configuration_dedicated_io_6 */
 240                                 <0x0000011c 0x000a282a>,        /* Register: configuration_dedicated_io_7 */
 241                                 <0x00000120 0x000a282a>,        /* Register: configuration_dedicated_io_8 */
 242                                 <0x00000124 0x000a282a>,        /* Register: configuration_dedicated_io_9 */
 243                                 <0x00000128 0x00090000>,        /* Register: configuration_dedicated_io_10 */
 244                                 <0x0000012c 0x00090000>,        /* Register: configuration_dedicated_io_11 */
 245                                 <0x00000130 0x000b282a>,        /* Register: configuration_dedicated_io_12 */
 246                                 <0x00000134 0x000b282a>,        /* Register: configuration_dedicated_io_13 */
 247                                 <0x00000138 0x000b282a>,        /* Register: configuration_dedicated_io_14 */
 248                                 <0x0000013c 0x000b282a>,        /* Register: configuration_dedicated_io_15 */
 249                                 <0x00000140 0x0008282a>,        /* Register: configuration_dedicated_io_16 */
 250                                 <0x00000144 0x000a282a>;        /* Register: configuration_dedicated_io_17 */
 251                 };
 252
 253                 /* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
 254                 fpga {
 255                         u-boot,dm-pre-reloc;
 256                         reg = <0xffd07400 0x00000100>;
 257                         pinctrl-single,register-width = <32>;
 258                         pinctrl-single,function-mask = <0x00000001>;
 259                         pinctrl-single,pins =
 260                                 <0x00000000 0x00000000>,        /* Register: pinmux_emac0_usefpga */
 261                                 <0x00000004 0x00000000>,        /* Register: pinmux_emac1_usefpga */
 262                                 <0x00000008 0x00000000>,        /* Register: pinmux_emac2_usefpga */
 263                                 <0x0000000c 0x00000000>,        /* Register: pinmux_i2c0_usefpga */
 264                                 <0x00000010 0x00000000>,        /* Register: pinmux_i2c1_usefpga */
 265                                 <0x00000014 0x00000000>,        /* Register: pinmux_i2c_emac0_usefpga */
 266                                 <0x00000018 0x00000000>,        /* Register: pinmux_i2c_emac1_usefpga */
 267                                 <0x0000001c 0x00000000>,        /* Register: pinmux_i2c_emac2_usefpga */
 268                                 <0x00000020 0x00000000>,        /* Register: pinmux_nand_usefpga */
 269                                 <0x00000024 0x00000000>,        /* Register: pinmux_qspi_usefpga */
 270                                 <0x00000028 0x00000000>,        /* Register: pinmux_sdmmc_usefpga */
 271                                 <0x0000002c 0x00000000>,        /* Register: pinmux_spim0_usefpga */
 272                                 <0x00000030 0x00000000>,        /* Register: pinmux_spim1_usefpga */
 273                                 <0x00000034 0x00000000>,        /* Register: pinmux_spis0_usefpga */
 274                                 <0x00000038 0x00000000>,        /* Register: pinmux_spis1_usefpga */
 275                                 <0x0000003c 0x00000000>,        /* Register: pinmux_uart0_usefpga */
 276                                 <0x00000040 0x00000000>;        /* Register: pinmux_uart1_usefpga */
 277                 };
 278         };
 279
 280         /*
 281          * Driver: altera_arria10_soc_noc_arria10_uboot_driver
 282          * Version: 1.0
 283          * Binding: device
 284          */
 285         i_noc: noc@0xffd10000 {
 286                 u-boot,dm-pre-reloc;
 287                 compatible = "altr,socfpga-a10-noc";
 288                 reg = <0xffd10000 0x00008000>;
 289                 reg-names = "mpu_m0";
 290
 291                 firewall {
 292                         u-boot,dm-pre-reloc;
 293                         /*
 294                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
 295                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
 296                          */
 297                         mpu0 = <0x00000000 0x0000ffff>;
 298                         /*
 299                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.base
 300                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.hpsregion0addr.limit
 301                          */
 302                         l3-0 = <0x00000000 0x0000ffff>;
 303                         /*
 304                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.base
 305                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram0region0addr.limit
 306                          */
 307                         fpga2sdram0-0 = <0x00000000 0x0000ffff>;
 308                         /*
 309                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.base
 310                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram1region0addr.limit
 311                          */
 312                         fpga2sdram1-0 = <0x00000000 0x0000ffff>;
 313                         /*
 314                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.base
 315                          * Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.fpga2sdram2region0addr.limit
 316                          */
 317                         fpga2sdram2-0 = <0x00000000 0x0000ffff>;
 318                 };
 319         };
 320
 321         hps_fpgabridge0: fpgabridge@0 {
 322                 compatible = "altr,socfpga-hps2fpga-bridge";
 323                 init-val = <1>;
 324         };
 325
 326         hps_fpgabridge1: fpgabridge@1 {
 327                 compatible = "altr,socfpga-lwhps2fpga-bridge";
 328                 init-val = <1>;
 329         };
 330
 331         hps_fpgabridge2: fpgabridge@2 {
 332                 compatible = "altr,socfpga-fpga2hps-bridge";
 333                 init-val = <1>;
 334         };
 335
 336         hps_fpgabridge3: fpgabridge@3 {
 337                 compatible = "altr,socfpga-fpga2sdram0-bridge";
 338                 init-val = <1>;
 339         };
 340
 341         hps_fpgabridge4: fpgabridge@4 {
 342                 compatible = "altr,socfpga-fpga2sdram1-bridge";
 343                 init-val = <0>;
 344         };
 345
 346         hps_fpgabridge5: fpgabridge@5 {
 347                 compatible = "altr,socfpga-fpga2sdram2-bridge";
 348                 init-val = <1>;
 349         };
 350 };