arch/arm/dts/socfpga_arria10.dtsi

   1 /*
   2  * Copyright Altera Corporation (C) 2014. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "altr,socfpga-a10-smp";
  28
  29                 cpu@0 {
  30                         compatible = "arm,cortex-a9";
  31                         device_type = "cpu";
  32                         reg = <0>;
  33                         next-level-cache = <&L2>;
  34                 };
  35                 cpu@1 {
  36                         compatible = "arm,cortex-a9";
  37                         device_type = "cpu";
  38                         reg = <1>;
  39                         next-level-cache = <&L2>;
  40                 };
  41         };
  42
  43         intc: intc@ffffd000 {
  44                 compatible = "arm,cortex-a9-gic";
  45                 #interrupt-cells = <3>;
  46                 interrupt-controller;
  47                 reg = <0xffffd000 0x1000>,
  48                       <0xffffc100 0x100>;
  49         };
  50
  51         soc {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 compatible = "simple-bus";
  55                 device_type = "soc";
  56                 interrupt-parent = <&intc>;
  57                 ranges;
  58                 u-boot,dm-pre-reloc;
  59
  60                 amba {
  61                         compatible = "simple-bus";
  62                         #address-cells = <1>;
  63                         #size-cells = <1>;
  64                         ranges;
  65
  66                         pdma: pdma@ffda1000 {
  67                                 compatible = "arm,pl330", "arm,primecell";
  68                                 reg = <0xffda1000 0x1000>;
  69                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  70                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  71                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  72                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  73                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  74                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  75                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  76                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  77                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  78                                 #dma-cells = <1>;
  79                                 #dma-channels = <8>;
  80                                 #dma-requests = <32>;
  81                                 clocks = <&l4_main_clk>;
  82                                 clock-names = "apb_pclk";
  83                         };
  84                 };
  85
  86                 base_fpga_region {
  87                         #address-cells = <0x1>;
  88                         #size-cells = <0x1>;
  89
  90                         compatible = "fpga-region";
  91                         fpga-mgr = <&fpga_mgr>;
  92                 };
  93
  94                 clkmgr@ffd04000 {
  95                                 compatible = "altr,clk-mgr";
  96                                 reg = <0xffd04000 0x1000>;
  97
  98                                 clocks {
  99                                         #address-cells = <1>;
 100                                         #size-cells = <0>;
 101
 102                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 103                                                 #clock-cells = <0>;
 104                                                 compatible = "fixed-clock";
 105                                         };
 106
 107                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
 108                                                 #clock-cells = <0>;
 109                                                 compatible = "fixed-clock";
 110                                         };
 111
 112                                         f2s_free_clk: f2s_free_clk {
 113                                                 #clock-cells = <0>;
 114                                                 compatible = "fixed-clock";
 115                                         };
 116
 117                                         osc1: osc1 {
 118                                                 #clock-cells = <0>;
 119                                                 compatible = "fixed-clock";
 120                                         };
 121
 122                                         main_pll: main_pll@40 {
 123                                                 #address-cells = <1>;
 124                                                 #size-cells = <0>;
 125                                                 #clock-cells = <0>;
 126                                                 compatible = "altr,socfpga-a10-pll-clock";
 127                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 128                                                          <&f2s_free_clk>;
 129                                                 reg = <0x40>;
 130
 131                                                 main_mpu_base_clk: main_mpu_base_clk {
 132                                                         #clock-cells = <0>;
 133                                                         compatible = "altr,socfpga-a10-perip-clk";
 134                                                         clocks = <&main_pll>;
 135                                                         div-reg = <0x140 0 11>;
 136                                                 };
 137
 138                                                 main_noc_base_clk: main_noc_base_clk {
 139                                                         #clock-cells = <0>;
 140                                                         compatible = "altr,socfpga-a10-perip-clk";
 141                                                         clocks = <&main_pll>;
 142                                                         div-reg = <0x144 0 11>;
 143                                                 };
 144
 145                                                 main_emaca_clk: main_emaca_clk@68 {
 146                                                         #clock-cells = <0>;
 147                                                         compatible = "altr,socfpga-a10-perip-clk";
 148                                                         clocks = <&main_pll>;
 149                                                         reg = <0x68>;
 150                                                 };
 151
 152                                                 main_emacb_clk: main_emacb_clk@6c {
 153                                                         #clock-cells = <0>;
 154                                                         compatible = "altr,socfpga-a10-perip-clk";
 155                                                         clocks = <&main_pll>;
 156                                                         reg = <0x6C>;
 157                                                 };
 158
 159                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
 160                                                         #clock-cells = <0>;
 161                                                         compatible = "altr,socfpga-a10-perip-clk";
 162                                                         clocks = <&main_pll>;
 163                                                         reg = <0x70>;
 164                                                 };
 165
 166                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
 167                                                         #clock-cells = <0>;
 168                                                         compatible = "altr,socfpga-a10-perip-clk";
 169                                                         clocks = <&main_pll>;
 170                                                         reg = <0x74>;
 171                                                 };
 172
 173                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
 174                                                         #clock-cells = <0>;
 175                                                         compatible = "altr,socfpga-a10-perip-clk"
 176 ;
 177                                                         clocks = <&main_pll>;
 178                                                         reg = <0x78>;
 179                                                 };
 180
 181                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
 182                                                         #clock-cells = <0>;
 183                                                         compatible = "altr,socfpga-a10-perip-clk";
 184                                                         clocks = <&main_pll>;
 185                                                         reg = <0x7C>;
 186                                                 };
 187
 188                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
 189                                                         #clock-cells = <0>;
 190                                                         compatible = "altr,socfpga-a10-perip-clk";
 191                                                         clocks = <&main_pll>;
 192                                                         reg = <0x80>;
 193                                                 };
 194
 195                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
 196                                                         #clock-cells = <0>;
 197                                                         compatible = "altr,socfpga-a10-perip-clk";
 198                                                         clocks = <&main_pll>;
 199                                                         reg = <0x84>;
 200                                                 };
 201
 202                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
 203                                                         #clock-cells = <0>;
 204                                                         compatible = "altr,socfpga-a10-perip-clk";
 205                                                         clocks = <&main_pll>;
 206                                                         reg = <0x9C>;
 207                                                 };
 208                                         };
 209
 210                                         periph_pll: periph_pll@c0 {
 211                                                 #address-cells = <1>;
 212                                                 #size-cells = <0>;
 213                                                 #clock-cells = <0>;
 214                                                 compatible = "altr,socfpga-a10-pll-clock";
 215                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 216                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 217                                                 reg = <0xC0>;
 218
 219                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 220                                                         #clock-cells = <0>;
 221                                                         compatible = "altr,socfpga-a10-perip-clk";
 222                                                         clocks = <&periph_pll>;
 223                                                         div-reg = <0x140 16 11>;
 224                                                 };
 225
 226                                                 peri_noc_base_clk: peri_noc_base_clk {
 227                                                         #clock-cells = <0>;
 228                                                         compatible = "altr,socfpga-a10-perip-clk";
 229                                                         clocks = <&periph_pll>;
 230                                                         div-reg = <0x144 16 11>;
 231                                                 };
 232
 233                                                 peri_emaca_clk: peri_emaca_clk@e8 {
 234                                                         #clock-cells = <0>;
 235                                                         compatible = "altr,socfpga-a10-perip-clk";
 236                                                         clocks = <&periph_pll>;
 237                                                         reg = <0xE8>;
 238                                                 };
 239
 240                                                 peri_emacb_clk: peri_emacb_clk@ec {
 241                                                         #clock-cells = <0>;
 242                                                         compatible = "altr,socfpga-a10-perip-clk";
 243                                                         clocks = <&periph_pll>;
 244                                                         reg = <0xEC>;
 245                                                 };
 246
 247                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
 248                                                         #clock-cells = <0>;
 249                                                         compatible = "altr,socfpga-a10-perip-clk";
 250                                                         clocks = <&periph_pll>;
 251                                                         reg = <0xF0>;
 252                                                 };
 253
 254                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
 255                                                         #clock-cells = <0>;
 256                                                         compatible = "altr,socfpga-a10-perip-clk";
 257                                                         clocks = <&periph_pll>;
 258                                                         reg = <0xF4>;
 259                                                 };
 260
 261                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
 262                                                         #clock-cells = <0>;
 263                                                         compatible = "altr,socfpga-a10-perip-clk";
 264                                                         clocks = <&periph_pll>;
 265                                                         reg = <0xF8>;
 266                                                 };
 267
 268                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
 269                                                         #clock-cells = <0>;
 270                                                         compatible = "altr,socfpga-a10-perip-clk";
 271                                                         clocks = <&periph_pll>;
 272                                                         reg = <0xFC>;
 273                                                 };
 274
 275                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
 276                                                         #clock-cells = <0>;
 277                                                         compatible = "altr,socfpga-a10-perip-clk";
 278                                                         clocks = <&periph_pll>;
 279                                                         reg = <0x100>;
 280                                                 };
 281
 282                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
 283                                                         #clock-cells = <0>;
 284                                                         compatible = "altr,socfpga-a10-perip-clk";
 285                                                         clocks = <&periph_pll>;
 286                                                         reg = <0x104>;
 287                                                 };
 288                                         };
 289
 290                                         mpu_free_clk: mpu_free_clk@60 {
 291                                                 #clock-cells = <0>;
 292                                                 compatible = "altr,socfpga-a10-perip-clk";
 293                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 294                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 295                                                          <&f2s_free_clk>;
 296                                                 reg = <0x60>;
 297                                         };
 298
 299                                         noc_free_clk: noc_free_clk@64 {
 300                                                 #clock-cells = <0>;
 301                                                 compatible = "altr,socfpga-a10-perip-clk";
 302                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 303                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 304                                                          <&f2s_free_clk>;
 305                                                 reg = <0x64>;
 306                                         };
 307
 308                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
 309                                                 #clock-cells = <0>;
 310                                                 compatible = "altr,socfpga-a10-perip-clk";
 311                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 312                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 313                                                          <&f2s_free_clk>;
 314                                                 reg = <0x104>;
 315                                         };
 316
 317                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
 318                                                 #clock-cells = <0>;
 319                                                 compatible = "altr,socfpga-a10-perip-clk";
 320                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 321                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 322                                                          <&f2s_free_clk>;
 323                                                 fixed-divider = <4>;
 324                                                 reg = <0xF8>;
 325                                         };
 326
 327                                         l4_sys_free_clk: l4_sys_free_clk {
 328                                                 #clock-cells = <0>;
 329                                                 compatible = "altr,socfpga-a10-perip-clk";
 330                                                 clocks = <&noc_free_clk>;
 331                                                 fixed-divider = <4>;
 332                                         };
 333
 334                                         l4_main_clk: l4_main_clk {
 335                                                 #clock-cells = <0>;
 336                                                 compatible = "altr,socfpga-a10-gate-clk";
 337                                                 clocks = <&noc_free_clk>;
 338                                                 div-reg = <0xA8 0 2>;
 339                                                 clk-gate = <0x48 1>;
 340                                         };
 341
 342                                         l4_mp_clk: l4_mp_clk {
 343                                                 #clock-cells = <0>;
 344                                                 compatible = "altr,socfpga-a10-gate-clk";
 345                                                 clocks = <&noc_free_clk>;
 346                                                 div-reg = <0xA8 8 2>;
 347                                                 clk-gate = <0x48 2>;
 348                                         };
 349
 350                                         l4_sp_clk: l4_sp_clk {
 351                                                 #clock-cells = <0>;
 352                                                 compatible = "altr,socfpga-a10-gate-clk";
 353                                                 clocks = <&noc_free_clk>;
 354                                                 div-reg = <0xA8 16 2>;
 355                                                 clk-gate = <0x48 3>;
 356                                         };
 357
 358                                         mpu_periph_clk: mpu_periph_clk {
 359                                                 #clock-cells = <0>;
 360                                                 compatible = "altr,socfpga-a10-gate-clk";
 361                                                 clocks = <&mpu_free_clk>;
 362                                                 fixed-divider = <4>;
 363                                                 clk-gate = <0x48 0>;
 364                                         };
 365
 366                                         sdmmc_clk: sdmmc_clk {
 367                                                 #clock-cells = <0>;
 368                                                 compatible = "altr,socfpga-a10-gate-clk";
 369                                                 clocks = <&sdmmc_free_clk>;
 370                                                 clk-gate = <0xC8 5>;
 371                                                 clk-phase = <0 135>;
 372                                         };
 373
 374                                         qspi_clk: qspi_clk {
 375                                                 #clock-cells = <0>;
 376                                                 compatible = "altr,socfpga-a10-gate-clk";
 377                                                 clocks = <&l4_main_clk>;
 378                                                 clk-gate = <0xC8 11>;
 379                                         };
 380
 381                                         nand_clk: nand_clk {
 382                                                 #clock-cells = <0>;
 383                                                 compatible = "altr,socfpga-a10-gate-clk";
 384                                                 clocks = <&l4_mp_clk>;
 385                                                 clk-gate = <0xC8 10>;
 386                                         };
 387
 388                                         spi_m_clk: spi_m_clk {
 389                                                 #clock-cells = <0>;
 390                                                 compatible = "altr,socfpga-a10-gate-clk";
 391                                                 clocks = <&l4_main_clk>;
 392                                                 clk-gate = <0xC8 9>;
 393                                         };
 394
 395                                         usb_clk: usb_clk {
 396                                                 #clock-cells = <0>;
 397                                                 compatible = "altr,socfpga-a10-gate-clk";
 398                                                 clocks = <&l4_mp_clk>;
 399                                                 clk-gate = <0xC8 8>;
 400                                         };
 401
 402                                         s2f_usr1_clk: s2f_usr1_clk {
 403                                                 #clock-cells = <0>;
 404                                                 compatible = "altr,socfpga-a10-gate-clk";
 405                                                 clocks = <&peri_s2f_usr1_clk>;
 406                                                 clk-gate = <0xC8 6>;
 407                                         };
 408                                 };
 409                 };
 410
 411                 socfpga_axi_setup: stmmac-axi-config {
 412                         snps,wr_osr_lmt = <0xf>;
 413                         snps,rd_osr_lmt = <0xf>;
 414                         snps,blen = <0 0 0 0 16 0 0>;
 415                 };
 416
 417                 gmac0: ethernet@ff800000 {
 418                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 419                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 420                         reg = <0xff800000 0x2000>;
 421                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 422                         interrupt-names = "macirq";
 423                         /* Filled in by bootloader */
 424                         mac-address = [00 00 00 00 00 00];
 425                         snps,multicast-filter-bins = <256>;
 426                         snps,perfect-filter-entries = <128>;
 427                         tx-fifo-depth = <4096>;
 428                         rx-fifo-depth = <16384>;
 429                         clocks = <&l4_mp_clk>;
 430                         clock-names = "stmmaceth";
 431                         resets = <&rst EMAC0_RESET>;
 432                         reset-names = "stmmaceth";
 433                         snps,axi-config = <&socfpga_axi_setup>;
 434                         status = "disabled";
 435                 };
 436
 437                 gmac1: ethernet@ff802000 {
 438                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 439                         altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 440                         reg = <0xff802000 0x2000>;
 441                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 442                         interrupt-names = "macirq";
 443                         /* Filled in by bootloader */
 444                         mac-address = [00 00 00 00 00 00];
 445                         snps,multicast-filter-bins = <256>;
 446                         snps,perfect-filter-entries = <128>;
 447                         tx-fifo-depth = <4096>;
 448                         rx-fifo-depth = <16384>;
 449                         clocks = <&l4_mp_clk>;
 450                         clock-names = "stmmaceth";
 451                         resets = <&rst EMAC1_RESET>;
 452                         reset-names = "stmmaceth";
 453                         snps,axi-config = <&socfpga_axi_setup>;
 454                         status = "disabled";
 455                 };
 456
 457                 gmac2: ethernet@ff804000 {
 458                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 459                         altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
 460                         reg = <0xff804000 0x2000>;
 461                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 462                         interrupt-names = "macirq";
 463                         /* Filled in by bootloader */
 464                         mac-address = [00 00 00 00 00 00];
 465                         snps,multicast-filter-bins = <256>;
 466                         snps,perfect-filter-entries = <128>;
 467                         tx-fifo-depth = <4096>;
 468                         rx-fifo-depth = <16384>;
 469                         clocks = <&l4_mp_clk>;
 470                         clock-names = "stmmaceth";
 471                         snps,axi-config = <&socfpga_axi_setup>;
 472                         status = "disabled";
 473                 };
 474
 475                 gpio0: gpio@ffc02900 {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         compatible = "snps,dw-apb-gpio";
 479                         reg = <0xffc02900 0x100>;
 480                         status = "disabled";
 481
 482                         porta: gpio-controller@0 {
 483                                 compatible = "snps,dw-apb-gpio-port";
 484                                 bank-name = "porta";
 485                                 gpio-controller;
 486                                 #gpio-cells = <2>;
 487                                 snps,nr-gpios = <29>;
 488                                 reg = <0>;
 489                                 interrupt-controller;
 490                                 #interrupt-cells = <2>;
 491                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 492                         };
 493                 };
 494
 495                 gpio1: gpio@ffc02a00 {
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         compatible = "snps,dw-apb-gpio";
 499                         reg = <0xffc02a00 0x100>;
 500                         status = "disabled";
 501
 502                         portb: gpio-controller@0 {
 503                                 compatible = "snps,dw-apb-gpio-port";
 504                                 bank-name = "portb";
 505                                 gpio-controller;
 506                                 #gpio-cells = <2>;
 507                                 snps,nr-gpios = <29>;
 508                                 reg = <0>;
 509                                 interrupt-controller;
 510                                 #interrupt-cells = <2>;
 511                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 512                         };
 513                 };
 514
 515                 gpio2: gpio@ffc02b00 {
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                         compatible = "snps,dw-apb-gpio";
 519                         reg = <0xffc02b00 0x100>;
 520                         status = "disabled";
 521
 522                         portc: gpio-controller@0 {
 523                                 compatible = "snps,dw-apb-gpio-port";
 524                                 bank-name = "portc";
 525                                 gpio-controller;
 526                                 #gpio-cells = <2>;
 527                                 snps,nr-gpios = <27>;
 528                                 reg = <0>;
 529                                 interrupt-controller;
 530                                 #interrupt-cells = <2>;
 531                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 532                         };
 533                 };
 534
 535                 fpga_mgr: fpga-mgr@ffd03000 {
 536                         compatible = "altr,socfpga-a10-fpga-mgr";
 537                         reg = <0xffd03000 0x100
 538                                0xffcfe400 0x20>;
 539                         clocks = <&l4_mp_clk>;
 540                         resets = <&rst FPGAMGR_RESET>;
 541                         reset-names = "fpgamgr";
 542                 };
 543
 544                 i2c0: i2c@ffc02200 {
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         compatible = "snps,designware-i2c";
 548                         reg = <0xffc02200 0x100>;
 549                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&l4_sp_clk>;
 551                         status = "disabled";
 552                 };
 553
 554                 i2c1: i2c@ffc02300 {
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                         compatible = "snps,designware-i2c";
 558                         reg = <0xffc02300 0x100>;
 559                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&l4_sp_clk>;
 561                         status = "disabled";
 562                 };
 563
 564                 i2c2: i2c@ffc02400 {
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         compatible = "snps,designware-i2c";
 568                         reg = <0xffc02400 0x100>;
 569                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 570                         clocks = <&l4_sp_clk>;
 571                         status = "disabled";
 572                 };
 573
 574                 i2c3: i2c@ffc02500 {
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                         compatible = "snps,designware-i2c";
 578                         reg = <0xffc02500 0x100>;
 579                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&l4_sp_clk>;
 581                         status = "disabled";
 582                 };
 583
 584                 i2c4: i2c@ffc02600 {
 585                         #address-cells = <1>;
 586                         #size-cells = <0>;
 587                         compatible = "snps,designware-i2c";
 588                         reg = <0xffc02600 0x100>;
 589                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&l4_sp_clk>;
 591                         status = "disabled";
 592                 };
 593
 594                 spi1: spi@ffda5000 {
 595                         compatible = "snps,dw-apb-ssi";
 596                         #address-cells = <1>;
 597                         #size-cells = <0>;
 598                         reg = <0xffda5000 0x100>;
 599                         interrupts = <0 102 4>;
 600                         num-chipselect = <4>;
 601                         bus-num = <0>;
 602                         /*32bit_access;*/
 603                         tx-dma-channel = <&pdma 16>;
 604                         rx-dma-channel = <&pdma 17>;
 605                         clocks = <&spi_m_clk>;
 606                         status = "disabled";
 607                 };
 608
 609                 sdr: sdr@ffc25000 {
 610                         compatible = "altr,sdr-ctl", "syscon";
 611                         reg = <0xffcfb100 0x80>;
 612                 };
 613
 614                 L2: l2-cache@fffff000 {
 615                         compatible = "arm,pl310-cache";
 616                         reg = <0xfffff000 0x1000>;
 617                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 618                         cache-unified;
 619                         cache-level = <2>;
 620                         prefetch-data = <1>;
 621                         prefetch-instr = <1>;
 622                         arm,shared-override;
 623                 };
 624
 625                 mmc: dwmmc0@ff808000 {
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                         compatible = "altr,socfpga-dw-mshc";
 629                         reg = <0xff808000 0x1000>;
 630                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 631                         fifo-depth = <0x400>;
 632                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 633                         clock-names = "biu", "ciu";
 634                         status = "disabled";
 635                 };
 636
 637                 nand: nand@ffb90000 {
 638                         #address-cells = <1>;
 639                         #size-cells = <1>;
 640                         compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
 641                         reg = <0xffb90000 0x20>,
 642                               <0xffb80000 0x1000>;
 643                         reg-names = "nand_data", "denali_reg";
 644                         interrupts = <0 99 4>;
 645                         dma-mask = <0xffffffff>;
 646                         clocks = <&nand_clk>;
 647                         status = "disabled";
 648                 };
 649
 650                 ocram: sram@ffe00000 {
 651                         compatible = "mmio-sram";
 652                         reg = <0xffe00000 0x40000>;
 653                 };
 654
 655                 eccmgr: eccmgr {
 656                         compatible = "altr,socfpga-a10-ecc-manager";
 657                         altr,sysmgr-syscon = <&sysmgr>;
 658                         #address-cells = <1>;
 659                         #size-cells = <1>;
 660                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 662                         interrupt-controller;
 663                         #interrupt-cells = <2>;
 664                         ranges;
 665
 666                         sdramedac {
 667                                 compatible = "altr,sdram-edac-a10";
 668                                 altr,sdr-syscon = <&sdr>;
 669                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
 670                                              <49 IRQ_TYPE_LEVEL_HIGH>;
 671                         };
 672
 673                         l2-ecc@ffd06010 {
 674                                 compatible = "altr,socfpga-a10-l2-ecc";
 675                                 reg = <0xffd06010 0x4>;
 676                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
 677                                              <32 IRQ_TYPE_LEVEL_HIGH>;
 678                         };
 679
 680                         ocram-ecc@ff8c3000 {
 681                                 compatible = "altr,socfpga-a10-ocram-ecc";
 682                                 reg = <0xff8c3000 0x400>;
 683                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 684                                              <33 IRQ_TYPE_LEVEL_HIGH>;
 685                         };
 686
 687                         emac0-rx-ecc@ff8c0800 {
 688                                 compatible = "altr,socfpga-eth-mac-ecc";
 689                                 reg = <0xff8c0800 0x400>;
 690                                 altr,ecc-parent = <&gmac0>;
 691                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 692                                              <36 IRQ_TYPE_LEVEL_HIGH>;
 693                         };
 694
 695                         emac0-tx-ecc@ff8c0c00 {
 696                                 compatible = "altr,socfpga-eth-mac-ecc";
 697                                 reg = <0xff8c0c00 0x400>;
 698                                 altr,ecc-parent = <&gmac0>;
 699                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 700                                              <37 IRQ_TYPE_LEVEL_HIGH>;
 701                         };
 702
 703                         dma-ecc@ff8c8000 {
 704                                 compatible = "altr,socfpga-dma-ecc";
 705                                 reg = <0xff8c8000 0x400>;
 706                                 altr,ecc-parent = <&pdma>;
 707                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
 708                                              <42 IRQ_TYPE_LEVEL_HIGH>;
 709                         };
 710
 711                         usb0-ecc@ff8c8800 {
 712                                 compatible = "altr,socfpga-usb-ecc";
 713                                 reg = <0xff8c8800 0x400>;
 714                                 altr,ecc-parent = <&usb0>;
 715                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
 716                                              <34 IRQ_TYPE_LEVEL_HIGH>;
 717                         };
 718                 };
 719
 720                 qspi: spi@ff809000 {
 721                         compatible = "cdns,qspi-nor", "cadence,qspi";
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                         reg = <0xff809000 0x100>,
 725                               <0xffa00000 0x100000>;
 726                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 727                         cdns,fifo-depth = <128>;
 728                         cdns,fifo-width = <4>;
 729                         cdns,trigger-address = <0x00000000>;
 730                         clocks = <&qspi_clk>;
 731                         status = "disabled";
 732                 };
 733
 734                 rst: rstmgr@ffd05000 {
 735                         #reset-cells = <1>;
 736                         compatible = "altr,rst-mgr";
 737                         reg = <0xffd05000 0x100>;
 738                         altr,modrst-offset = <0x20>;
 739                         u-boot,dm-pre-reloc;
 740                 };
 741
 742                 scu: snoop-control-unit@ffffc000 {
 743                         compatible = "arm,cortex-a9-scu";
 744                         reg = <0xffffc000 0x100>;
 745                 };
 746
 747                 sysmgr: sysmgr@ffd06000 {
 748                         compatible = "altr,sys-mgr", "syscon";
 749                         reg = <0xffd06000 0x300>;
 750                         cpu1-start-addr = <0xffd06230>;
 751                 };
 752
 753                 /* Local timer */
 754                 timer@ffffc600 {
 755                         compatible = "arm,cortex-a9-twd-timer";
 756                         reg = <0xffffc600 0x100>;
 757                         interrupts = <1 13 0xf04>;
 758                         clocks = <&mpu_periph_clk>;
 759                 };
 760
 761                 timer0: timer0@ffc02700 {
 762                         compatible = "snps,dw-apb-timer";
 763                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 764                         reg = <0xffc02700 0x100>;
 765                         clocks = <&l4_sp_clk>;
 766                         clock-names = "timer";
 767                 };
 768
 769                 timer1: timer1@ffc02800 {
 770                         compatible = "snps,dw-apb-timer";
 771                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 772                         reg = <0xffc02800 0x100>;
 773                         clocks = <&l4_sp_clk>;
 774                         clock-names = "timer";
 775                 };
 776
 777                 timer2: timer2@ffd00000 {
 778                         compatible = "snps,dw-apb-timer";
 779                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 780                         reg = <0xffd00000 0x100>;
 781                         clocks = <&l4_sys_free_clk>;
 782                         clock-names = "timer";
 783                 };
 784
 785                 timer3: timer3@ffd00100 {
 786                         compatible = "snps,dw-apb-timer";
 787                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 788                         reg = <0xffd01000 0x100>;
 789                         clocks = <&l4_sys_free_clk>;
 790                         clock-names = "timer";
 791                 };
 792
 793                 uart0: serial0@ffc02000 {
 794                         compatible = "snps,dw-apb-uart";
 795                         reg = <0xffc02000 0x100>;
 796                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 797                         reg-shift = <2>;
 798                         reg-io-width = <4>;
 799                         clocks = <&l4_sp_clk>;
 800                         status = "disabled";
 801                 };
 802
 803                 uart1: serial1@ffc02100 {
 804                         compatible = "snps,dw-apb-uart";
 805                         reg = <0xffc02100 0x100>;
 806                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 807                         reg-shift = <2>;
 808                         reg-io-width = <4>;
 809                         clocks = <&l4_sp_clk>;
 810                         status = "disabled";
 811                 };
 812
 813                 usbphy0: usbphy {
 814                         #phy-cells = <0>;
 815                         compatible = "usb-nop-xceiv";
 816                         status = "okay";
 817                 };
 818
 819                 usb0: usb@ffb00000 {
 820                         compatible = "snps,dwc2";
 821                         reg = <0xffb00000 0xffff>;
 822                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 823                         clocks = <&usb_clk>;
 824                         clock-names = "otg";
 825                         resets = <&rst USB0_RESET>;
 826                         reset-names = "dwc2";
 827                         phys = <&usbphy0>;
 828                         phy-names = "usb2-phy";
 829                         status = "disabled";
 830                 };
 831
 832                 usb1: usb@ffb40000 {
 833                         compatible = "snps,dwc2";
 834                         reg = <0xffb40000 0xffff>;
 835                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 836                         clocks = <&usb_clk>;
 837                         clock-names = "otg";
 838                         resets = <&rst USB1_RESET>;
 839                         reset-names = "dwc2";
 840                         phys = <&usbphy0>;
 841                         phy-names = "usb2-phy";
 842                         status = "disabled";
 843                 };
 844
 845                 watchdog0: watchdog@ffd00200 {
 846                         compatible = "snps,dw-wdt";
 847                         reg = <0xffd00200 0x100>;
 848                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 849                         clocks = <&l4_sys_free_clk>;
 850                         status = "disabled";
 851                 };
 852
 853                 watchdog1: watchdog@ffd00300 {
 854                         compatible = "snps,dw-wdt";
 855                         reg = <0xffd00300 0x100>;
 856                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 857                         clocks = <&l4_sys_free_clk>;
 858                         status = "disabled";
 859                 };
 860         };
 861 };