2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
32 enable-method = "altr,socfpga-a10-smp";
35 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
49 compatible = "arm,cortex-a9-gic";
50 #interrupt-cells = <3>;
52 reg = <0xffffd000 0x1000>,
59 compatible = "simple-bus";
61 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffda1000 0x1000>;
74 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
75 <0 84 IRQ_TYPE_LEVEL_HIGH>,
76 <0 85 IRQ_TYPE_LEVEL_HIGH>,
77 <0 86 IRQ_TYPE_LEVEL_HIGH>,
78 <0 87 IRQ_TYPE_LEVEL_HIGH>,
79 <0 88 IRQ_TYPE_LEVEL_HIGH>,
80 <0 89 IRQ_TYPE_LEVEL_HIGH>,
81 <0 90 IRQ_TYPE_LEVEL_HIGH>,
82 <0 91 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&l4_main_clk>;
87 clock-names = "apb_pclk";
92 #address-cells = <0x1>;
95 compatible = "fpga-region";
96 fpga-mgr = <&fpga_mgr>;
100 compatible = "altr,clk-mgr";
101 reg = <0xffd04000 0x1000>;
105 #address-cells = <1>;
109 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
111 compatible = "fixed-clock";
115 cb_intosc_ls_clk: cb_intosc_ls_clk {
117 compatible = "fixed-clock";
121 f2s_free_clk: f2s_free_clk {
123 compatible = "fixed-clock";
129 compatible = "fixed-clock";
133 main_pll: main_pll@40 {
134 #address-cells = <1>;
137 compatible = "altr,socfpga-a10-pll-clock";
138 clocks = <&osc1>, <&cb_intosc_ls_clk>,
143 main_mpu_base_clk: main_mpu_base_clk {
145 compatible = "altr,socfpga-a10-perip-clk";
146 clocks = <&main_pll>;
147 div-reg = <0x140 0 11>;
150 main_noc_base_clk: main_noc_base_clk {
152 compatible = "altr,socfpga-a10-perip-clk";
153 clocks = <&main_pll>;
154 div-reg = <0x144 0 11>;
158 main_emaca_clk: main_emaca_clk@68 {
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
165 main_emacb_clk: main_emacb_clk@6c {
167 compatible = "altr,socfpga-a10-perip-clk";
168 clocks = <&main_pll>;
172 main_emac_ptp_clk: main_emac_ptp_clk@70 {
174 compatible = "altr,socfpga-a10-perip-clk";
175 clocks = <&main_pll>;
179 main_gpio_db_clk: main_gpio_db_clk@74 {
181 compatible = "altr,socfpga-a10-perip-clk";
182 clocks = <&main_pll>;
186 main_sdmmc_clk: main_sdmmc_clk@78 {
188 compatible = "altr,socfpga-a10-perip-clk"
190 clocks = <&main_pll>;
194 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
201 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
203 compatible = "altr,socfpga-a10-perip-clk";
204 clocks = <&main_pll>;
208 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
210 compatible = "altr,socfpga-a10-perip-clk";
211 clocks = <&main_pll>;
215 main_periph_ref_clk: main_periph_ref_clk@9c {
217 compatible = "altr,socfpga-a10-perip-clk";
218 clocks = <&main_pll>;
223 periph_pll: periph_pll@c0 {
224 #address-cells = <1>;
227 compatible = "altr,socfpga-a10-pll-clock";
228 clocks = <&osc1>, <&cb_intosc_ls_clk>,
229 <&f2s_free_clk>, <&main_periph_ref_clk>;
233 peri_mpu_base_clk: peri_mpu_base_clk {
235 compatible = "altr,socfpga-a10-perip-clk";
236 clocks = <&periph_pll>;
237 div-reg = <0x140 16 11>;
240 peri_noc_base_clk: peri_noc_base_clk {
242 compatible = "altr,socfpga-a10-perip-clk";
243 clocks = <&periph_pll>;
244 div-reg = <0x144 16 11>;
248 peri_emaca_clk: peri_emaca_clk@e8 {
250 compatible = "altr,socfpga-a10-perip-clk";
251 clocks = <&periph_pll>;
255 peri_emacb_clk: peri_emacb_clk@ec {
257 compatible = "altr,socfpga-a10-perip-clk";
258 clocks = <&periph_pll>;
262 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
264 compatible = "altr,socfpga-a10-perip-clk";
265 clocks = <&periph_pll>;
269 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
271 compatible = "altr,socfpga-a10-perip-clk";
272 clocks = <&periph_pll>;
276 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
278 compatible = "altr,socfpga-a10-perip-clk";
279 clocks = <&periph_pll>;
283 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
285 compatible = "altr,socfpga-a10-perip-clk";
286 clocks = <&periph_pll>;
290 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
292 compatible = "altr,socfpga-a10-perip-clk";
293 clocks = <&periph_pll>;
297 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
299 compatible = "altr,socfpga-a10-perip-clk";
300 clocks = <&periph_pll>;
305 mpu_free_clk: mpu_free_clk@60 {
307 compatible = "altr,socfpga-a10-perip-clk";
308 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
309 <&osc1>, <&cb_intosc_hs_div2_clk>,
314 noc_free_clk: noc_free_clk@64 {
316 compatible = "altr,socfpga-a10-perip-clk";
317 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
318 <&osc1>, <&cb_intosc_hs_div2_clk>,
324 s2f_user1_free_clk: s2f_user1_free_clk@104 {
326 compatible = "altr,socfpga-a10-perip-clk";
327 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
328 <&osc1>, <&cb_intosc_hs_div2_clk>,
333 sdmmc_free_clk: sdmmc_free_clk@f8 {
335 compatible = "altr,socfpga-a10-perip-clk";
336 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
337 <&osc1>, <&cb_intosc_hs_div2_clk>,
343 l4_sys_free_clk: l4_sys_free_clk {
345 compatible = "altr,socfpga-a10-perip-clk";
346 clocks = <&noc_free_clk>;
351 l4_main_clk: l4_main_clk {
353 compatible = "altr,socfpga-a10-gate-clk";
354 clocks = <&noc_free_clk>;
355 div-reg = <0xA8 0 2>;
359 l4_mp_clk: l4_mp_clk {
361 compatible = "altr,socfpga-a10-gate-clk";
362 clocks = <&noc_free_clk>;
363 div-reg = <0xA8 8 2>;
367 l4_sp_clk: l4_sp_clk {
369 compatible = "altr,socfpga-a10-gate-clk";
370 clocks = <&noc_free_clk>;
371 div-reg = <0xA8 16 2>;
375 mpu_periph_clk: mpu_periph_clk {
377 compatible = "altr,socfpga-a10-gate-clk";
378 clocks = <&mpu_free_clk>;
383 sdmmc_clk: sdmmc_clk {
385 compatible = "altr,socfpga-a10-gate-clk";
386 clocks = <&sdmmc_free_clk>;
393 compatible = "altr,socfpga-a10-gate-clk";
394 clocks = <&l4_main_clk>;
395 clk-gate = <0xC8 11>;
400 compatible = "altr,socfpga-a10-gate-clk";
401 clocks = <&l4_mp_clk>;
402 clk-gate = <0xC8 10>;
405 spi_m_clk: spi_m_clk {
407 compatible = "altr,socfpga-a10-gate-clk";
408 clocks = <&l4_main_clk>;
414 compatible = "altr,socfpga-a10-gate-clk";
415 clocks = <&l4_mp_clk>;
419 s2f_usr1_clk: s2f_usr1_clk {
421 compatible = "altr,socfpga-a10-gate-clk";
422 clocks = <&peri_s2f_usr1_clk>;
428 socfpga_axi_setup: stmmac-axi-config {
429 snps,wr_osr_lmt = <0xf>;
430 snps,rd_osr_lmt = <0xf>;
431 snps,blen = <0 0 0 0 16 0 0>;
434 gmac0: ethernet@ff800000 {
435 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
436 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
437 reg = <0xff800000 0x2000>;
438 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
439 interrupt-names = "macirq";
440 /* Filled in by bootloader */
441 mac-address = [00 00 00 00 00 00];
442 snps,multicast-filter-bins = <256>;
443 snps,perfect-filter-entries = <128>;
444 tx-fifo-depth = <4096>;
445 rx-fifo-depth = <16384>;
446 clocks = <&l4_mp_clk>;
447 clock-names = "stmmaceth";
448 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
449 reset-names = "stmmaceth", "stmmaceth-ocp";
450 snps,axi-config = <&socfpga_axi_setup>;
454 gmac1: ethernet@ff802000 {
455 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
456 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
457 reg = <0xff802000 0x2000>;
458 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "macirq";
460 /* Filled in by bootloader */
461 mac-address = [00 00 00 00 00 00];
462 snps,multicast-filter-bins = <256>;
463 snps,perfect-filter-entries = <128>;
464 tx-fifo-depth = <4096>;
465 rx-fifo-depth = <16384>;
466 clocks = <&l4_mp_clk>;
467 clock-names = "stmmaceth";
468 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
469 reset-names = "stmmaceth", "stmmaceth-ocp";
470 snps,axi-config = <&socfpga_axi_setup>;
474 gmac2: ethernet@ff804000 {
475 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
476 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
477 reg = <0xff804000 0x2000>;
478 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
479 interrupt-names = "macirq";
480 /* Filled in by bootloader */
481 mac-address = [00 00 00 00 00 00];
482 snps,multicast-filter-bins = <256>;
483 snps,perfect-filter-entries = <128>;
484 tx-fifo-depth = <4096>;
485 rx-fifo-depth = <16384>;
486 clocks = <&l4_mp_clk>;
487 clock-names = "stmmaceth";
488 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
489 reset-names = "stmmaceth", "stmmaceth-ocp";
490 snps,axi-config = <&socfpga_axi_setup>;
494 gpio0: gpio@ffc02900 {
495 #address-cells = <1>;
497 compatible = "snps,dw-apb-gpio";
498 reg = <0xffc02900 0x100>;
501 porta: gpio-controller@0 {
502 compatible = "snps,dw-apb-gpio-port";
506 snps,nr-gpios = <29>;
508 interrupt-controller;
509 #interrupt-cells = <2>;
510 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
514 gpio1: gpio@ffc02a00 {
515 #address-cells = <1>;
517 compatible = "snps,dw-apb-gpio";
518 reg = <0xffc02a00 0x100>;
521 portb: gpio-controller@0 {
522 compatible = "snps,dw-apb-gpio-port";
526 snps,nr-gpios = <29>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
530 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
534 gpio2: gpio@ffc02b00 {
535 #address-cells = <1>;
537 compatible = "snps,dw-apb-gpio";
538 reg = <0xffc02b00 0x100>;
541 portc: gpio-controller@0 {
542 compatible = "snps,dw-apb-gpio-port";
546 snps,nr-gpios = <27>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
554 fpga_mgr: fpga-mgr@ffd03000 {
555 compatible = "altr,socfpga-a10-fpga-mgr";
556 reg = <0xffd03000 0x100
558 clocks = <&l4_mp_clk>;
559 resets = <&rst FPGAMGR_RESET>;
560 reset-names = "fpgamgr";
564 #address-cells = <1>;
566 compatible = "snps,designware-i2c";
567 reg = <0xffc02200 0x100>;
568 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&l4_sp_clk>;
570 resets = <&rst I2C0_RESET>;
576 #address-cells = <1>;
578 compatible = "snps,designware-i2c";
579 reg = <0xffc02300 0x100>;
580 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&l4_sp_clk>;
582 resets = <&rst I2C1_RESET>;
588 #address-cells = <1>;
590 compatible = "snps,designware-i2c";
591 reg = <0xffc02400 0x100>;
592 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&l4_sp_clk>;
594 resets = <&rst I2C2_RESET>;
600 #address-cells = <1>;
602 compatible = "snps,designware-i2c";
603 reg = <0xffc02500 0x100>;
604 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&l4_sp_clk>;
606 resets = <&rst I2C3_RESET>;
612 #address-cells = <1>;
614 compatible = "snps,designware-i2c";
615 reg = <0xffc02600 0x100>;
616 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&l4_sp_clk>;
618 resets = <&rst I2C4_RESET>;
624 compatible = "snps,dw-apb-ssi";
625 #address-cells = <1>;
627 reg = <0xffda5000 0x100>;
628 interrupts = <0 102 4>;
629 num-chipselect = <4>;
632 tx-dma-channel = <&pdma 16>;
633 rx-dma-channel = <&pdma 17>;
634 clocks = <&spi_m_clk>;
639 compatible = "altr,sdr-ctl", "syscon";
640 reg = <0xffcfb100 0x80>;
643 L2: l2-cache@fffff000 {
644 compatible = "arm,pl310-cache";
645 reg = <0xfffff000 0x1000>;
646 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
650 prefetch-instr = <1>;
654 mmc: dwmmc0@ff808000 {
655 #address-cells = <1>;
657 compatible = "altr,socfpga-dw-mshc";
658 reg = <0xff808000 0x1000>;
659 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
660 fifo-depth = <0x400>;
661 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
662 clock-names = "biu", "ciu";
663 resets = <&rst SDMMC_RESET>;
667 nand: nand@ffb90000 {
668 #address-cells = <1>;
670 compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
671 reg = <0xffb90000 0x20>,
673 reg-names = "nand_data", "denali_reg";
674 interrupts = <0 99 4>;
675 dma-mask = <0xffffffff>;
676 clocks = <&nand_clk>;
677 resets = <&rst NAND_RESET>;
681 ocram: sram@ffe00000 {
682 compatible = "mmio-sram";
683 reg = <0xffe00000 0x40000>;
687 compatible = "altr,socfpga-a10-ecc-manager";
688 altr,sysmgr-syscon = <&sysmgr>;
689 #address-cells = <1>;
691 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
692 <0 0 IRQ_TYPE_LEVEL_HIGH>;
693 interrupt-controller;
694 #interrupt-cells = <2>;
698 compatible = "altr,sdram-edac-a10";
699 altr,sdr-syscon = <&sdr>;
700 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
701 <49 IRQ_TYPE_LEVEL_HIGH>;
705 compatible = "altr,socfpga-a10-l2-ecc";
706 reg = <0xffd06010 0x4>;
707 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
708 <32 IRQ_TYPE_LEVEL_HIGH>;
712 compatible = "altr,socfpga-a10-ocram-ecc";
713 reg = <0xff8c3000 0x400>;
714 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
715 <33 IRQ_TYPE_LEVEL_HIGH>;
718 emac0-rx-ecc@ff8c0800 {
719 compatible = "altr,socfpga-eth-mac-ecc";
720 reg = <0xff8c0800 0x400>;
721 altr,ecc-parent = <&gmac0>;
722 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
723 <36 IRQ_TYPE_LEVEL_HIGH>;
726 emac0-tx-ecc@ff8c0c00 {
727 compatible = "altr,socfpga-eth-mac-ecc";
728 reg = <0xff8c0c00 0x400>;
729 altr,ecc-parent = <&gmac0>;
730 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
731 <37 IRQ_TYPE_LEVEL_HIGH>;
735 compatible = "altr,socfpga-dma-ecc";
736 reg = <0xff8c8000 0x400>;
737 altr,ecc-parent = <&pdma>;
738 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
739 <42 IRQ_TYPE_LEVEL_HIGH>;
743 compatible = "altr,socfpga-usb-ecc";
744 reg = <0xff8c8800 0x400>;
745 altr,ecc-parent = <&usb0>;
746 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
747 <34 IRQ_TYPE_LEVEL_HIGH>;
752 compatible = "cdns,qspi-nor";
753 #address-cells = <1>;
755 reg = <0xff809000 0x100>,
756 <0xffa00000 0x100000>;
757 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
758 cdns,fifo-depth = <128>;
759 cdns,fifo-width = <4>;
760 cdns,trigger-address = <0x00000000>;
761 clocks = <&qspi_clk>;
765 rst: rstmgr@ffd05000 {
767 compatible = "altr,rst-mgr";
768 reg = <0xffd05000 0x100>;
769 altr,modrst-offset = <0x20>;
773 scu: snoop-control-unit@ffffc000 {
774 compatible = "arm,cortex-a9-scu";
775 reg = <0xffffc000 0x100>;
778 sysmgr: sysmgr@ffd06000 {
779 compatible = "altr,sys-mgr", "syscon";
780 reg = <0xffd06000 0x300>;
781 cpu1-start-addr = <0xffd06230>;
786 compatible = "arm,cortex-a9-twd-timer";
787 reg = <0xffffc600 0x100>;
788 interrupts = <1 13 0xf04>;
789 clocks = <&mpu_periph_clk>;
792 timer0: timer0@ffc02700 {
793 compatible = "snps,dw-apb-timer";
794 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
795 reg = <0xffc02700 0x100>;
796 clocks = <&l4_sp_clk>;
797 clock-names = "timer";
800 timer1: timer1@ffc02800 {
801 compatible = "snps,dw-apb-timer";
802 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
803 reg = <0xffc02800 0x100>;
804 clocks = <&l4_sp_clk>;
805 clock-names = "timer";
808 timer2: timer2@ffd00000 {
809 compatible = "snps,dw-apb-timer";
810 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
811 reg = <0xffd00000 0x100>;
812 clocks = <&l4_sys_free_clk>;
813 clock-names = "timer";
817 timer3: timer3@ffd00100 {
818 compatible = "snps,dw-apb-timer";
819 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
820 reg = <0xffd01000 0x100>;
821 clocks = <&l4_sys_free_clk>;
822 clock-names = "timer";
825 uart0: serial0@ffc02000 {
826 compatible = "snps,dw-apb-uart";
827 reg = <0xffc02000 0x100>;
828 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&l4_sp_clk>;
832 resets = <&rst UART0_RESET>;
836 uart1: serial1@ffc02100 {
837 compatible = "snps,dw-apb-uart";
838 reg = <0xffc02100 0x100>;
839 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&l4_sp_clk>;
843 resets = <&rst UART1_RESET>;
849 compatible = "usb-nop-xceiv";
854 compatible = "snps,dwc2";
855 reg = <0xffb00000 0xffff>;
856 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
859 resets = <&rst USB0_RESET>;
860 reset-names = "dwc2";
862 phy-names = "usb2-phy";
867 compatible = "snps,dwc2";
868 reg = <0xffb40000 0xffff>;
869 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
872 resets = <&rst USB1_RESET>;
873 reset-names = "dwc2";
875 phy-names = "usb2-phy";
879 watchdog0: watchdog@ffd00200 {
880 compatible = "snps,dw-wdt";
881 reg = <0xffd00200 0x100>;
882 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&l4_sys_free_clk>;
887 watchdog1: watchdog@ffd00300 {
888 compatible = "snps,dw-wdt";
889 reg = <0xffd00300 0x100>;
890 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&l4_sys_free_clk>;