arch/arm/dts/socfpga_arria10.dtsi

   1 /*
   2  * Copyright Altera Corporation (C) 2014. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         chosen {
  25                 tick-timer = &timer2;
  26                 u-boot,dm-pre-reloc;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32                 enable-method = "altr,socfpga-a10-smp";
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         reg = <0>;
  38                         next-level-cache = <&L2>;
  39                 };
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         intc: intc@ffffd000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 #interrupt-cells = <3>;
  51                 interrupt-controller;
  52                 reg = <0xffffd000 0x1000>,
  53                       <0xffffc100 0x100>;
  54         };
  55
  56         soc {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "simple-bus";
  60                 device_type = "soc";
  61                 interrupt-parent = <&intc>;
  62                 ranges;
  63                 u-boot,dm-pre-reloc;
  64
  65                 amba {
  66                         compatible = "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         ranges;
  70
  71                         pdma: pdma@ffda1000 {
  72                                 compatible = "arm,pl330", "arm,primecell";
  73                                 reg = <0xffda1000 0x1000>;
  74                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  75                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  76                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  77                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  78                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  79                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  80                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  81                                              <0 90 IRQ_TYPE_LEVEL_HIGH>,
  82                                              <0 91 IRQ_TYPE_LEVEL_HIGH>;
  83                                 #dma-cells = <1>;
  84                                 #dma-channels = <8>;
  85                                 #dma-requests = <32>;
  86                                 clocks = <&l4_main_clk>;
  87                                 clock-names = "apb_pclk";
  88                         };
  89                 };
  90
  91                 base_fpga_region {
  92                         #address-cells = <0x1>;
  93                         #size-cells = <0x1>;
  94
  95                         compatible = "fpga-region";
  96                         fpga-mgr = <&fpga_mgr>;
  97                 };
  98
  99                 clkmgr@ffd04000 {
 100                                 compatible = "altr,clk-mgr";
 101                                 reg = <0xffd04000 0x1000>;
 102                                 u-boot,dm-pre-reloc;
 103
 104                                 clocks {
 105                                         #address-cells = <1>;
 106                                         #size-cells = <0>;
 107                                         u-boot,dm-pre-reloc;
 108
 109                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
 110                                                 #clock-cells = <0>;
 111                                                 compatible = "fixed-clock";
 112                                                 u-boot,dm-pre-reloc;
 113                                         };
 114
 115                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
 116                                                 #clock-cells = <0>;
 117                                                 compatible = "fixed-clock";
 118                                                 u-boot,dm-pre-reloc;
 119                                         };
 120
 121                                         f2s_free_clk: f2s_free_clk {
 122                                                 #clock-cells = <0>;
 123                                                 compatible = "fixed-clock";
 124                                                 u-boot,dm-pre-reloc;
 125                                         };
 126
 127                                         osc1: osc1 {
 128                                                 #clock-cells = <0>;
 129                                                 compatible = "fixed-clock";
 130                                                 u-boot,dm-pre-reloc;
 131                                         };
 132
 133                                         main_pll: main_pll@40 {
 134                                                 #address-cells = <1>;
 135                                                 #size-cells = <0>;
 136                                                 #clock-cells = <0>;
 137                                                 compatible = "altr,socfpga-a10-pll-clock";
 138                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 139                                                          <&f2s_free_clk>;
 140                                                 reg = <0x40>;
 141                                                 u-boot,dm-pre-reloc;
 142
 143                                                 main_mpu_base_clk: main_mpu_base_clk {
 144                                                         #clock-cells = <0>;
 145                                                         compatible = "altr,socfpga-a10-perip-clk";
 146                                                         clocks = <&main_pll>;
 147                                                         div-reg = <0x140 0 11>;
 148                                                 };
 149
 150                                                 main_noc_base_clk: main_noc_base_clk {
 151                                                         #clock-cells = <0>;
 152                                                         compatible = "altr,socfpga-a10-perip-clk";
 153                                                         clocks = <&main_pll>;
 154                                                         div-reg = <0x144 0 11>;
 155                                                         u-boot,dm-pre-reloc;
 156                                                 };
 157
 158                                                 main_emaca_clk: main_emaca_clk@68 {
 159                                                         #clock-cells = <0>;
 160                                                         compatible = "altr,socfpga-a10-perip-clk";
 161                                                         clocks = <&main_pll>;
 162                                                         reg = <0x68>;
 163                                                 };
 164
 165                                                 main_emacb_clk: main_emacb_clk@6c {
 166                                                         #clock-cells = <0>;
 167                                                         compatible = "altr,socfpga-a10-perip-clk";
 168                                                         clocks = <&main_pll>;
 169                                                         reg = <0x6C>;
 170                                                 };
 171
 172                                                 main_emac_ptp_clk: main_emac_ptp_clk@70 {
 173                                                         #clock-cells = <0>;
 174                                                         compatible = "altr,socfpga-a10-perip-clk";
 175                                                         clocks = <&main_pll>;
 176                                                         reg = <0x70>;
 177                                                 };
 178
 179                                                 main_gpio_db_clk: main_gpio_db_clk@74 {
 180                                                         #clock-cells = <0>;
 181                                                         compatible = "altr,socfpga-a10-perip-clk";
 182                                                         clocks = <&main_pll>;
 183                                                         reg = <0x74>;
 184                                                 };
 185
 186                                                 main_sdmmc_clk: main_sdmmc_clk@78 {
 187                                                         #clock-cells = <0>;
 188                                                         compatible = "altr,socfpga-a10-perip-clk"
 189 ;
 190                                                         clocks = <&main_pll>;
 191                                                         reg = <0x78>;
 192                                                 };
 193
 194                                                 main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
 195                                                         #clock-cells = <0>;
 196                                                         compatible = "altr,socfpga-a10-perip-clk";
 197                                                         clocks = <&main_pll>;
 198                                                         reg = <0x7C>;
 199                                                 };
 200
 201                                                 main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
 202                                                         #clock-cells = <0>;
 203                                                         compatible = "altr,socfpga-a10-perip-clk";
 204                                                         clocks = <&main_pll>;
 205                                                         reg = <0x80>;
 206                                                 };
 207
 208                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
 209                                                         #clock-cells = <0>;
 210                                                         compatible = "altr,socfpga-a10-perip-clk";
 211                                                         clocks = <&main_pll>;
 212                                                         reg = <0x84>;
 213                                                 };
 214
 215                                                 main_periph_ref_clk: main_periph_ref_clk@9c {
 216                                                         #clock-cells = <0>;
 217                                                         compatible = "altr,socfpga-a10-perip-clk";
 218                                                         clocks = <&main_pll>;
 219                                                         reg = <0x9C>;
 220                                                 };
 221                                         };
 222
 223                                         periph_pll: periph_pll@c0 {
 224                                                 #address-cells = <1>;
 225                                                 #size-cells = <0>;
 226                                                 #clock-cells = <0>;
 227                                                 compatible = "altr,socfpga-a10-pll-clock";
 228                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 229                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 230                                                 reg = <0xC0>;
 231                                                 u-boot,dm-pre-reloc;
 232
 233                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 234                                                         #clock-cells = <0>;
 235                                                         compatible = "altr,socfpga-a10-perip-clk";
 236                                                         clocks = <&periph_pll>;
 237                                                         div-reg = <0x140 16 11>;
 238                                                 };
 239
 240                                                 peri_noc_base_clk: peri_noc_base_clk {
 241                                                         #clock-cells = <0>;
 242                                                         compatible = "altr,socfpga-a10-perip-clk";
 243                                                         clocks = <&periph_pll>;
 244                                                         div-reg = <0x144 16 11>;
 245                                                         u-boot,dm-pre-reloc;
 246                                                 };
 247
 248                                                 peri_emaca_clk: peri_emaca_clk@e8 {
 249                                                         #clock-cells = <0>;
 250                                                         compatible = "altr,socfpga-a10-perip-clk";
 251                                                         clocks = <&periph_pll>;
 252                                                         reg = <0xE8>;
 253                                                 };
 254
 255                                                 peri_emacb_clk: peri_emacb_clk@ec {
 256                                                         #clock-cells = <0>;
 257                                                         compatible = "altr,socfpga-a10-perip-clk";
 258                                                         clocks = <&periph_pll>;
 259                                                         reg = <0xEC>;
 260                                                 };
 261
 262                                                 peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
 263                                                         #clock-cells = <0>;
 264                                                         compatible = "altr,socfpga-a10-perip-clk";
 265                                                         clocks = <&periph_pll>;
 266                                                         reg = <0xF0>;
 267                                                 };
 268
 269                                                 peri_gpio_db_clk: peri_gpio_db_clk@f4 {
 270                                                         #clock-cells = <0>;
 271                                                         compatible = "altr,socfpga-a10-perip-clk";
 272                                                         clocks = <&periph_pll>;
 273                                                         reg = <0xF4>;
 274                                                 };
 275
 276                                                 peri_sdmmc_clk: peri_sdmmc_clk@f8 {
 277                                                         #clock-cells = <0>;
 278                                                         compatible = "altr,socfpga-a10-perip-clk";
 279                                                         clocks = <&periph_pll>;
 280                                                         reg = <0xF8>;
 281                                                 };
 282
 283                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
 284                                                         #clock-cells = <0>;
 285                                                         compatible = "altr,socfpga-a10-perip-clk";
 286                                                         clocks = <&periph_pll>;
 287                                                         reg = <0xFC>;
 288                                                 };
 289
 290                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
 291                                                         #clock-cells = <0>;
 292                                                         compatible = "altr,socfpga-a10-perip-clk";
 293                                                         clocks = <&periph_pll>;
 294                                                         reg = <0x100>;
 295                                                 };
 296
 297                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
 298                                                         #clock-cells = <0>;
 299                                                         compatible = "altr,socfpga-a10-perip-clk";
 300                                                         clocks = <&periph_pll>;
 301                                                         reg = <0x104>;
 302                                                 };
 303                                         };
 304
 305                                         mpu_free_clk: mpu_free_clk@60 {
 306                                                 #clock-cells = <0>;
 307                                                 compatible = "altr,socfpga-a10-perip-clk";
 308                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 309                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 310                                                          <&f2s_free_clk>;
 311                                                 reg = <0x60>;
 312                                         };
 313
 314                                         noc_free_clk: noc_free_clk@64 {
 315                                                 #clock-cells = <0>;
 316                                                 compatible = "altr,socfpga-a10-perip-clk";
 317                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 318                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 319                                                          <&f2s_free_clk>;
 320                                                 reg = <0x64>;
 321                                                 u-boot,dm-pre-reloc;
 322                                         };
 323
 324                                         s2f_user1_free_clk: s2f_user1_free_clk@104 {
 325                                                 #clock-cells = <0>;
 326                                                 compatible = "altr,socfpga-a10-perip-clk";
 327                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 328                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 329                                                          <&f2s_free_clk>;
 330                                                 reg = <0x104>;
 331                                         };
 332
 333                                         sdmmc_free_clk: sdmmc_free_clk@f8 {
 334                                                 #clock-cells = <0>;
 335                                                 compatible = "altr,socfpga-a10-perip-clk";
 336                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 337                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 338                                                          <&f2s_free_clk>;
 339                                                 fixed-divider = <4>;
 340                                                 reg = <0xF8>;
 341                                         };
 342
 343                                         l4_sys_free_clk: l4_sys_free_clk {
 344                                                 #clock-cells = <0>;
 345                                                 compatible = "altr,socfpga-a10-perip-clk";
 346                                                 clocks = <&noc_free_clk>;
 347                                                 fixed-divider = <4>;
 348                                                 u-boot,dm-pre-reloc;
 349                                         };
 350
 351                                         l4_main_clk: l4_main_clk {
 352                                                 #clock-cells = <0>;
 353                                                 compatible = "altr,socfpga-a10-gate-clk";
 354                                                 clocks = <&noc_free_clk>;
 355                                                 div-reg = <0xA8 0 2>;
 356                                                 clk-gate = <0x48 1>;
 357                                         };
 358
 359                                         l4_mp_clk: l4_mp_clk {
 360                                                 #clock-cells = <0>;
 361                                                 compatible = "altr,socfpga-a10-gate-clk";
 362                                                 clocks = <&noc_free_clk>;
 363                                                 div-reg = <0xA8 8 2>;
 364                                                 clk-gate = <0x48 2>;
 365                                         };
 366
 367                                         l4_sp_clk: l4_sp_clk {
 368                                                 #clock-cells = <0>;
 369                                                 compatible = "altr,socfpga-a10-gate-clk";
 370                                                 clocks = <&noc_free_clk>;
 371                                                 div-reg = <0xA8 16 2>;
 372                                                 clk-gate = <0x48 3>;
 373                                         };
 374
 375                                         mpu_periph_clk: mpu_periph_clk {
 376                                                 #clock-cells = <0>;
 377                                                 compatible = "altr,socfpga-a10-gate-clk";
 378                                                 clocks = <&mpu_free_clk>;
 379                                                 fixed-divider = <4>;
 380                                                 clk-gate = <0x48 0>;
 381                                         };
 382
 383                                         sdmmc_clk: sdmmc_clk {
 384                                                 #clock-cells = <0>;
 385                                                 compatible = "altr,socfpga-a10-gate-clk";
 386                                                 clocks = <&sdmmc_free_clk>;
 387                                                 clk-gate = <0xC8 5>;
 388                                                 clk-phase = <0 135>;
 389                                         };
 390
 391                                         qspi_clk: qspi_clk {
 392                                                 #clock-cells = <0>;
 393                                                 compatible = "altr,socfpga-a10-gate-clk";
 394                                                 clocks = <&l4_main_clk>;
 395                                                 clk-gate = <0xC8 11>;
 396                                         };
 397
 398                                         nand_clk: nand_clk {
 399                                                 #clock-cells = <0>;
 400                                                 compatible = "altr,socfpga-a10-gate-clk";
 401                                                 clocks = <&l4_mp_clk>;
 402                                                 clk-gate = <0xC8 10>;
 403                                         };
 404
 405                                         spi_m_clk: spi_m_clk {
 406                                                 #clock-cells = <0>;
 407                                                 compatible = "altr,socfpga-a10-gate-clk";
 408                                                 clocks = <&l4_main_clk>;
 409                                                 clk-gate = <0xC8 9>;
 410                                         };
 411
 412                                         usb_clk: usb_clk {
 413                                                 #clock-cells = <0>;
 414                                                 compatible = "altr,socfpga-a10-gate-clk";
 415                                                 clocks = <&l4_mp_clk>;
 416                                                 clk-gate = <0xC8 8>;
 417                                         };
 418
 419                                         s2f_usr1_clk: s2f_usr1_clk {
 420                                                 #clock-cells = <0>;
 421                                                 compatible = "altr,socfpga-a10-gate-clk";
 422                                                 clocks = <&peri_s2f_usr1_clk>;
 423                                                 clk-gate = <0xC8 6>;
 424                                         };
 425                                 };
 426                 };
 427
 428                 socfpga_axi_setup: stmmac-axi-config {
 429                         snps,wr_osr_lmt = <0xf>;
 430                         snps,rd_osr_lmt = <0xf>;
 431                         snps,blen = <0 0 0 0 16 0 0>;
 432                 };
 433
 434                 gmac0: ethernet@ff800000 {
 435                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 436                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
 437                         reg = <0xff800000 0x2000>;
 438                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 439                         interrupt-names = "macirq";
 440                         /* Filled in by bootloader */
 441                         mac-address = [00 00 00 00 00 00];
 442                         snps,multicast-filter-bins = <256>;
 443                         snps,perfect-filter-entries = <128>;
 444                         tx-fifo-depth = <4096>;
 445                         rx-fifo-depth = <16384>;
 446                         clocks = <&l4_mp_clk>;
 447                         clock-names = "stmmaceth";
 448                         resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
 449                         reset-names = "stmmaceth", "stmmaceth-ocp";
 450                         snps,axi-config = <&socfpga_axi_setup>;
 451                         status = "disabled";
 452                 };
 453
 454                 gmac1: ethernet@ff802000 {
 455                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 456                         altr,sysmgr-syscon = <&sysmgr 0x48 0>;
 457                         reg = <0xff802000 0x2000>;
 458                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 459                         interrupt-names = "macirq";
 460                         /* Filled in by bootloader */
 461                         mac-address = [00 00 00 00 00 00];
 462                         snps,multicast-filter-bins = <256>;
 463                         snps,perfect-filter-entries = <128>;
 464                         tx-fifo-depth = <4096>;
 465                         rx-fifo-depth = <16384>;
 466                         clocks = <&l4_mp_clk>;
 467                         clock-names = "stmmaceth";
 468                         resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
 469                         reset-names = "stmmaceth", "stmmaceth-ocp";
 470                         snps,axi-config = <&socfpga_axi_setup>;
 471                         status = "disabled";
 472                 };
 473
 474                 gmac2: ethernet@ff804000 {
 475                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 476                         altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
 477                         reg = <0xff804000 0x2000>;
 478                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 479                         interrupt-names = "macirq";
 480                         /* Filled in by bootloader */
 481                         mac-address = [00 00 00 00 00 00];
 482                         snps,multicast-filter-bins = <256>;
 483                         snps,perfect-filter-entries = <128>;
 484                         tx-fifo-depth = <4096>;
 485                         rx-fifo-depth = <16384>;
 486                         clocks = <&l4_mp_clk>;
 487                         clock-names = "stmmaceth";
 488                         resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
 489                         reset-names = "stmmaceth", "stmmaceth-ocp";
 490                         snps,axi-config = <&socfpga_axi_setup>;
 491                         status = "disabled";
 492                 };
 493
 494                 gpio0: gpio@ffc02900 {
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         compatible = "snps,dw-apb-gpio";
 498                         reg = <0xffc02900 0x100>;
 499                         status = "disabled";
 500
 501                         porta: gpio-controller@0 {
 502                                 compatible = "snps,dw-apb-gpio-port";
 503                                 bank-name = "porta";
 504                                 gpio-controller;
 505                                 #gpio-cells = <2>;
 506                                 snps,nr-gpios = <29>;
 507                                 reg = <0>;
 508                                 interrupt-controller;
 509                                 #interrupt-cells = <2>;
 510                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 511                         };
 512                 };
 513
 514                 gpio1: gpio@ffc02a00 {
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                         compatible = "snps,dw-apb-gpio";
 518                         reg = <0xffc02a00 0x100>;
 519                         status = "disabled";
 520
 521                         portb: gpio-controller@0 {
 522                                 compatible = "snps,dw-apb-gpio-port";
 523                                 bank-name = "portb";
 524                                 gpio-controller;
 525                                 #gpio-cells = <2>;
 526                                 snps,nr-gpios = <29>;
 527                                 reg = <0>;
 528                                 interrupt-controller;
 529                                 #interrupt-cells = <2>;
 530                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 531                         };
 532                 };
 533
 534                 gpio2: gpio@ffc02b00 {
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         compatible = "snps,dw-apb-gpio";
 538                         reg = <0xffc02b00 0x100>;
 539                         status = "disabled";
 540
 541                         portc: gpio-controller@0 {
 542                                 compatible = "snps,dw-apb-gpio-port";
 543                                 bank-name = "portc";
 544                                 gpio-controller;
 545                                 #gpio-cells = <2>;
 546                                 snps,nr-gpios = <27>;
 547                                 reg = <0>;
 548                                 interrupt-controller;
 549                                 #interrupt-cells = <2>;
 550                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 551                         };
 552                 };
 553
 554                 fpga_mgr: fpga-mgr@ffd03000 {
 555                         compatible = "altr,socfpga-a10-fpga-mgr";
 556                         reg = <0xffd03000 0x100
 557                                0xffcfe400 0x20>;
 558                         clocks = <&l4_mp_clk>;
 559                         resets = <&rst FPGAMGR_RESET>;
 560                         reset-names = "fpgamgr";
 561                 };
 562
 563                 i2c0: i2c@ffc02200 {
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         compatible = "snps,designware-i2c";
 567                         reg = <0xffc02200 0x100>;
 568                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 569                         clocks = <&l4_sp_clk>;
 570                         resets = <&rst I2C0_RESET>;
 571                         reset-names = "i2c";
 572                         status = "disabled";
 573                 };
 574
 575                 i2c1: i2c@ffc02300 {
 576                         #address-cells = <1>;
 577                         #size-cells = <0>;
 578                         compatible = "snps,designware-i2c";
 579                         reg = <0xffc02300 0x100>;
 580                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 581                         clocks = <&l4_sp_clk>;
 582                         resets = <&rst I2C1_RESET>;
 583                         reset-names = "i2c";
 584                         status = "disabled";
 585                 };
 586
 587                 i2c2: i2c@ffc02400 {
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                         compatible = "snps,designware-i2c";
 591                         reg = <0xffc02400 0x100>;
 592                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 593                         clocks = <&l4_sp_clk>;
 594                         resets = <&rst I2C2_RESET>;
 595                         reset-names = "i2c";
 596                         status = "disabled";
 597                 };
 598
 599                 i2c3: i2c@ffc02500 {
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                         compatible = "snps,designware-i2c";
 603                         reg = <0xffc02500 0x100>;
 604                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&l4_sp_clk>;
 606                         resets = <&rst I2C3_RESET>;
 607                         reset-names = "i2c";
 608                         status = "disabled";
 609                 };
 610
 611                 i2c4: i2c@ffc02600 {
 612                         #address-cells = <1>;
 613                         #size-cells = <0>;
 614                         compatible = "snps,designware-i2c";
 615                         reg = <0xffc02600 0x100>;
 616                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 617                         clocks = <&l4_sp_clk>;
 618                         resets = <&rst I2C4_RESET>;
 619                         reset-names = "i2c";
 620                         status = "disabled";
 621                 };
 622
 623                 spi1: spi@ffda5000 {
 624                         compatible = "snps,dw-apb-ssi";
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         reg = <0xffda5000 0x100>;
 628                         interrupts = <0 102 4>;
 629                         num-chipselect = <4>;
 630                         bus-num = <0>;
 631                         /*32bit_access;*/
 632                         tx-dma-channel = <&pdma 16>;
 633                         rx-dma-channel = <&pdma 17>;
 634                         clocks = <&spi_m_clk>;
 635                         status = "disabled";
 636                 };
 637
 638                 sdr: sdr@ffc25000 {
 639                         compatible = "altr,sdr-ctl", "syscon";
 640                         reg = <0xffcfb100 0x80>;
 641                 };
 642
 643                 L2: l2-cache@fffff000 {
 644                         compatible = "arm,pl310-cache";
 645                         reg = <0xfffff000 0x1000>;
 646                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 647                         cache-unified;
 648                         cache-level = <2>;
 649                         prefetch-data = <1>;
 650                         prefetch-instr = <1>;
 651                         arm,shared-override;
 652                 };
 653
 654                 mmc: dwmmc0@ff808000 {
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         compatible = "altr,socfpga-dw-mshc";
 658                         reg = <0xff808000 0x1000>;
 659                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 660                         fifo-depth = <0x400>;
 661                         clocks = <&l4_mp_clk>, <&sdmmc_clk>;
 662                         clock-names = "biu", "ciu";
 663                         status = "disabled";
 664                 };
 665
 666                 nand: nand@ffb90000 {
 667                         #address-cells = <1>;
 668                         #size-cells = <1>;
 669                         compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
 670                         reg = <0xffb90000 0x20>,
 671                               <0xffb80000 0x1000>;
 672                         reg-names = "nand_data", "denali_reg";
 673                         interrupts = <0 99 4>;
 674                         dma-mask = <0xffffffff>;
 675                         clocks = <&nand_clk>;
 676                         resets = <&rst NAND_RESET>;
 677                         status = "disabled";
 678                 };
 679
 680                 ocram: sram@ffe00000 {
 681                         compatible = "mmio-sram";
 682                         reg = <0xffe00000 0x40000>;
 683                 };
 684
 685                 eccmgr: eccmgr {
 686                         compatible = "altr,socfpga-a10-ecc-manager";
 687                         altr,sysmgr-syscon = <&sysmgr>;
 688                         #address-cells = <1>;
 689                         #size-cells = <1>;
 690                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
 692                         interrupt-controller;
 693                         #interrupt-cells = <2>;
 694                         ranges;
 695
 696                         sdramedac {
 697                                 compatible = "altr,sdram-edac-a10";
 698                                 altr,sdr-syscon = <&sdr>;
 699                                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
 700                                              <49 IRQ_TYPE_LEVEL_HIGH>;
 701                         };
 702
 703                         l2-ecc@ffd06010 {
 704                                 compatible = "altr,socfpga-a10-l2-ecc";
 705                                 reg = <0xffd06010 0x4>;
 706                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
 707                                              <32 IRQ_TYPE_LEVEL_HIGH>;
 708                         };
 709
 710                         ocram-ecc@ff8c3000 {
 711                                 compatible = "altr,socfpga-a10-ocram-ecc";
 712                                 reg = <0xff8c3000 0x400>;
 713                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 714                                              <33 IRQ_TYPE_LEVEL_HIGH>;
 715                         };
 716
 717                         emac0-rx-ecc@ff8c0800 {
 718                                 compatible = "altr,socfpga-eth-mac-ecc";
 719                                 reg = <0xff8c0800 0x400>;
 720                                 altr,ecc-parent = <&gmac0>;
 721                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
 722                                              <36 IRQ_TYPE_LEVEL_HIGH>;
 723                         };
 724
 725                         emac0-tx-ecc@ff8c0c00 {
 726                                 compatible = "altr,socfpga-eth-mac-ecc";
 727                                 reg = <0xff8c0c00 0x400>;
 728                                 altr,ecc-parent = <&gmac0>;
 729                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
 730                                              <37 IRQ_TYPE_LEVEL_HIGH>;
 731                         };
 732
 733                         dma-ecc@ff8c8000 {
 734                                 compatible = "altr,socfpga-dma-ecc";
 735                                 reg = <0xff8c8000 0x400>;
 736                                 altr,ecc-parent = <&pdma>;
 737                                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
 738                                              <42 IRQ_TYPE_LEVEL_HIGH>;
 739                         };
 740
 741                         usb0-ecc@ff8c8800 {
 742                                 compatible = "altr,socfpga-usb-ecc";
 743                                 reg = <0xff8c8800 0x400>;
 744                                 altr,ecc-parent = <&usb0>;
 745                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
 746                                              <34 IRQ_TYPE_LEVEL_HIGH>;
 747                         };
 748                 };
 749
 750                 qspi: spi@ff809000 {
 751                         compatible = "cdns,qspi-nor";
 752                         #address-cells = <1>;
 753                         #size-cells = <0>;
 754                         reg = <0xff809000 0x100>,
 755                               <0xffa00000 0x100000>;
 756                         interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
 757                         cdns,fifo-depth = <128>;
 758                         cdns,fifo-width = <4>;
 759                         cdns,trigger-address = <0x00000000>;
 760                         clocks = <&qspi_clk>;
 761                         status = "disabled";
 762                 };
 763
 764                 rst: rstmgr@ffd05000 {
 765                         #reset-cells = <1>;
 766                         compatible = "altr,rst-mgr";
 767                         reg = <0xffd05000 0x100>;
 768                         altr,modrst-offset = <0x20>;
 769                         u-boot,dm-pre-reloc;
 770                 };
 771
 772                 scu: snoop-control-unit@ffffc000 {
 773                         compatible = "arm,cortex-a9-scu";
 774                         reg = <0xffffc000 0x100>;
 775                 };
 776
 777                 sysmgr: sysmgr@ffd06000 {
 778                         compatible = "altr,sys-mgr", "syscon";
 779                         reg = <0xffd06000 0x300>;
 780                         cpu1-start-addr = <0xffd06230>;
 781                 };
 782
 783                 /* Local timer */
 784                 timer@ffffc600 {
 785                         compatible = "arm,cortex-a9-twd-timer";
 786                         reg = <0xffffc600 0x100>;
 787                         interrupts = <1 13 0xf04>;
 788                         clocks = <&mpu_periph_clk>;
 789                 };
 790
 791                 timer0: timer0@ffc02700 {
 792                         compatible = "snps,dw-apb-timer";
 793                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 794                         reg = <0xffc02700 0x100>;
 795                         clocks = <&l4_sp_clk>;
 796                         clock-names = "timer";
 797                 };
 798
 799                 timer1: timer1@ffc02800 {
 800                         compatible = "snps,dw-apb-timer";
 801                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 802                         reg = <0xffc02800 0x100>;
 803                         clocks = <&l4_sp_clk>;
 804                         clock-names = "timer";
 805                 };
 806
 807                 timer2: timer2@ffd00000 {
 808                         compatible = "snps,dw-apb-timer";
 809                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 810                         reg = <0xffd00000 0x100>;
 811                         clocks = <&l4_sys_free_clk>;
 812                         clock-names = "timer";
 813                         u-boot,dm-pre-reloc;
 814                 };
 815
 816                 timer3: timer3@ffd00100 {
 817                         compatible = "snps,dw-apb-timer";
 818                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 819                         reg = <0xffd01000 0x100>;
 820                         clocks = <&l4_sys_free_clk>;
 821                         clock-names = "timer";
 822                 };
 823
 824                 uart0: serial0@ffc02000 {
 825                         compatible = "snps,dw-apb-uart";
 826                         reg = <0xffc02000 0x100>;
 827                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 828                         reg-shift = <2>;
 829                         reg-io-width = <4>;
 830                         clocks = <&l4_sp_clk>;
 831                         resets = <&rst UART0_RESET>;
 832                         status = "disabled";
 833                 };
 834
 835                 uart1: serial1@ffc02100 {
 836                         compatible = "snps,dw-apb-uart";
 837                         reg = <0xffc02100 0x100>;
 838                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 839                         reg-shift = <2>;
 840                         reg-io-width = <4>;
 841                         clocks = <&l4_sp_clk>;
 842                         resets = <&rst UART1_RESET>;
 843                         status = "disabled";
 844                 };
 845
 846                 usbphy0: usbphy {
 847                         #phy-cells = <0>;
 848                         compatible = "usb-nop-xceiv";
 849                         status = "okay";
 850                 };
 851
 852                 usb0: usb@ffb00000 {
 853                         compatible = "snps,dwc2";
 854                         reg = <0xffb00000 0xffff>;
 855                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 856                         clocks = <&usb_clk>;
 857                         clock-names = "otg";
 858                         resets = <&rst USB0_RESET>;
 859                         reset-names = "dwc2";
 860                         phys = <&usbphy0>;
 861                         phy-names = "usb2-phy";
 862                         status = "disabled";
 863                 };
 864
 865                 usb1: usb@ffb40000 {
 866                         compatible = "snps,dwc2";
 867                         reg = <0xffb40000 0xffff>;
 868                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 869                         clocks = <&usb_clk>;
 870                         clock-names = "otg";
 871                         resets = <&rst USB1_RESET>;
 872                         reset-names = "dwc2";
 873                         phys = <&usbphy0>;
 874                         phy-names = "usb2-phy";
 875                         status = "disabled";
 876                 };
 877
 878                 watchdog0: watchdog@ffd00200 {
 879                         compatible = "snps,dw-wdt";
 880                         reg = <0xffd00200 0x100>;
 881                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 882                         clocks = <&l4_sys_free_clk>;
 883                         status = "disabled";
 884                 };
 885
 886                 watchdog1: watchdog@ffd00300 {
 887                         compatible = "snps,dw-wdt";
 888                         reg = <0xffd00300 0x100>;
 889                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 890                         clocks = <&l4_sys_free_clk>;
 891                         status = "disabled";
 892                 };
 893         };
 894 };