1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019, Intel Corporation
5 #include "socfpga_agilex.dtsi"
8 model = "SoCFPGA Agilex SoCDK";
18 stdout-path = "serial0:115200n8";
22 compatible = "gpio-leds";
25 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
30 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
35 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
40 device_type = "memory";
41 /* We expect the bootloader to fill in the reg */
48 clock-frequency = <25000000>;
63 max-frame-size = <9000>;
68 compatible = "snps,dwmac-mdio";
69 phy0: ethernet-phy@0 {
72 txd0-skew-ps = <0>; /* -420ps */
73 txd1-skew-ps = <0>; /* -420ps */
74 txd2-skew-ps = <0>; /* -420ps */
75 txd3-skew-ps = <0>; /* -420ps */
76 rxd0-skew-ps = <420>; /* 0ps */
77 rxd1-skew-ps = <420>; /* 0ps */
78 rxd2-skew-ps = <420>; /* 0ps */
79 rxd3-skew-ps = <420>; /* 0ps */
80 txen-skew-ps = <0>; /* -420ps */
81 txc-skew-ps = <900>; /* 0ps */
82 rxdv-skew-ps = <420>; /* 0ps */
83 rxc-skew-ps = <1680>; /* 780ps */
101 disable-over-current;
110 #address-cells = <1>;
112 compatible = "mt25qu02g";
114 spi-max-frequency = <100000000>;
117 cdns,page-size = <256>;
118 cdns,block-size = <16>;
119 cdns,read-delay = <1>;
120 cdns,tshsl-ns = <50>;
121 cdns,tsd2d-ns = <50>;
126 compatible = "fixed-partitions";
127 #address-cells = <1>;
130 qspi_boot: partition@0 {
131 label = "Boot and fpga data";
132 reg = <0x0 0x034B0000>;
135 qspi_rootfs: partition@34B0000 {
136 label = "Root Filesystem - JFFS2";
137 reg = <0x034B0000 0x0EB50000>;