1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019, Intel Corporation
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
21 service_reserved: svcbuffer@0 {
22 compatible = "shared-dma-pool";
23 reg = <0x0 0x0 0x0 0x1000000>;
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
63 compatible = "arm,armv8-pmuv3";
64 interrupts = <0 170 4>,
68 interrupt-affinity = <&cpu0>,
72 interrupt-parent = <&intc>;
76 compatible = "arm,psci-0.2";
81 compatible = "arm,gic-400", "arm,cortex-a15-gic";
82 #interrupt-cells = <3>;
84 reg = <0x0 0xfffc1000 0x0 0x1000>,
85 <0x0 0xfffc2000 0x0 0x2000>,
86 <0x0 0xfffc4000 0x0 0x2000>,
87 <0x0 0xfffc6000 0x0 0x2000>;
93 compatible = "simple-bus";
95 interrupt-parent = <&intc>;
96 ranges = <0 0 0 0xffffffff>;
99 #address-cells = <0x1>;
101 compatible = "fpga-region";
102 fpga-mgr = <&fpga_mgr>;
105 clkmgr: clock-controller@ffd10000 {
106 compatible = "intel,agilex-clkmgr";
107 reg = <0xffd10000 0x1000>;
112 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
114 compatible = "fixed-clock";
117 cb_intosc_ls_clk: cb-intosc-ls-clk {
119 compatible = "fixed-clock";
122 f2s_free_clk: f2s-free-clk {
124 compatible = "fixed-clock";
129 compatible = "fixed-clock";
134 compatible = "fixed-clock";
135 clock-frequency = <200000000>;
138 gmac0: ethernet@ff800000 {
139 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
140 reg = <0xff800000 0x2000>;
141 interrupts = <0 90 4>;
142 interrupt-names = "macirq";
143 mac-address = [00 00 00 00 00 00];
144 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
145 reset-names = "stmmaceth", "stmmaceth-ocp";
146 tx-fifo-depth = <16384>;
147 rx-fifo-depth = <16384>;
148 snps,multicast-filter-bins = <256>;
150 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
151 clocks = <&clkmgr AGILEX_EMAC0_CLK>;
152 clock-names = "stmmaceth";
156 gmac1: ethernet@ff802000 {
157 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
158 reg = <0xff802000 0x2000>;
159 interrupts = <0 91 4>;
160 interrupt-names = "macirq";
161 mac-address = [00 00 00 00 00 00];
162 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
163 reset-names = "stmmaceth", "stmmaceth-ocp";
164 tx-fifo-depth = <16384>;
165 rx-fifo-depth = <16384>;
166 snps,multicast-filter-bins = <256>;
168 altr,sysmgr-syscon = <&sysmgr 0x48 8>;
169 clocks = <&clkmgr AGILEX_EMAC1_CLK>;
170 clock-names = "stmmaceth";
174 gmac2: ethernet@ff804000 {
175 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
176 reg = <0xff804000 0x2000>;
177 interrupts = <0 92 4>;
178 interrupt-names = "macirq";
179 mac-address = [00 00 00 00 00 00];
180 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
181 reset-names = "stmmaceth", "stmmaceth-ocp";
182 tx-fifo-depth = <16384>;
183 rx-fifo-depth = <16384>;
184 snps,multicast-filter-bins = <256>;
186 altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
187 clocks = <&clkmgr AGILEX_EMAC2_CLK>;
188 clock-names = "stmmaceth";
192 gpio0: gpio@ffc03200 {
193 #address-cells = <1>;
195 compatible = "snps,dw-apb-gpio";
196 reg = <0xffc03200 0x100>;
197 resets = <&rst GPIO0_RESET>;
200 porta: gpio-controller@0 {
201 compatible = "snps,dw-apb-gpio-port";
204 snps,nr-gpios = <24>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 interrupts = <0 110 4>;
212 gpio1: gpio@ffc03300 {
213 #address-cells = <1>;
215 compatible = "snps,dw-apb-gpio";
216 reg = <0xffc03300 0x100>;
217 resets = <&rst GPIO1_RESET>;
220 portb: gpio-controller@0 {
221 compatible = "snps,dw-apb-gpio-port";
224 snps,nr-gpios = <24>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 interrupts = <0 111 4>;
233 #address-cells = <1>;
235 compatible = "snps,designware-i2c";
236 reg = <0xffc02800 0x100>;
237 interrupts = <0 103 4>;
238 resets = <&rst I2C0_RESET>;
239 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
244 #address-cells = <1>;
246 compatible = "snps,designware-i2c";
247 reg = <0xffc02900 0x100>;
248 interrupts = <0 104 4>;
249 resets = <&rst I2C1_RESET>;
250 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
255 #address-cells = <1>;
257 compatible = "snps,designware-i2c";
258 reg = <0xffc02a00 0x100>;
259 interrupts = <0 105 4>;
260 resets = <&rst I2C2_RESET>;
261 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
266 #address-cells = <1>;
268 compatible = "snps,designware-i2c";
269 reg = <0xffc02b00 0x100>;
270 interrupts = <0 106 4>;
271 resets = <&rst I2C3_RESET>;
272 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
277 #address-cells = <1>;
279 compatible = "snps,designware-i2c";
280 reg = <0xffc02c00 0x100>;
281 interrupts = <0 107 4>;
282 resets = <&rst I2C4_RESET>;
283 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
287 mmc: dwmmc0@ff808000 {
288 #address-cells = <1>;
290 compatible = "altr,socfpga-dw-mshc";
291 reg = <0xff808000 0x1000>;
292 interrupts = <0 96 4>;
293 fifo-depth = <0x400>;
294 resets = <&rst SDMMC_RESET>;
295 reset-names = "reset";
296 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
297 <&clkmgr AGILEX_SDMMC_CLK>;
298 clock-names = "biu", "ciu";
303 nand: nand@ffb90000 {
304 #address-cells = <1>;
306 compatible = "altr,socfpga-denali-nand";
307 reg = <0xffb90000 0x10000>,
309 reg-names = "nand_data", "denali_reg";
310 interrupts = <0 97 4>;
311 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
315 ocram: sram@ffe00000 {
316 compatible = "mmio-sram";
317 reg = <0xffe00000 0x40000>;
320 pdma: pdma@ffda0000 {
321 compatible = "arm,pl330", "arm,primecell";
322 reg = <0xffda0000 0x1000>;
323 interrupts = <0 81 4>,
334 #dma-requests = <32>;
335 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
336 reset-names = "dma", "dma-ocp";
337 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
338 clock-names = "apb_pclk";
341 rst: rstmgr@ffd11000 {
343 compatible = "altr,stratix10-rst-mgr";
344 reg = <0xffd11000 0x100>;
347 smmu: iommu@fa000000 {
348 compatible = "arm,mmu-500", "arm,smmu-v2";
349 reg = <0xfa000000 0x40000>;
350 #global-interrupts = <2>;
352 interrupt-parent = <&intc>;
353 interrupts = <0 128 4>, /* Global Secure Fault */
354 <0 129 4>, /* Global Non-secure Fault */
355 /* Non-secure Context Interrupts (32) */
356 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
357 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
358 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
359 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
360 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
361 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
362 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
363 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
364 stream-match-mask = <0x7ff0>;
369 compatible = "snps,dw-apb-ssi";
370 #address-cells = <1>;
372 reg = <0xffda4000 0x1000>;
373 interrupts = <0 99 4>;
374 resets = <&rst SPIM0_RESET>;
377 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
382 compatible = "snps,dw-apb-ssi";
383 #address-cells = <1>;
385 reg = <0xffda5000 0x1000>;
386 interrupts = <0 100 4>;
387 resets = <&rst SPIM1_RESET>;
390 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
394 sysmgr: sysmgr@ffd12000 {
395 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
396 reg = <0xffd12000 0x500>;
401 compatible = "arm,armv8-timer";
402 interrupts = <1 13 0xf08>,
408 timer0: timer0@ffc03000 {
409 compatible = "snps,dw-apb-timer";
410 interrupts = <0 113 4>;
411 reg = <0xffc03000 0x100>;
412 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
413 clock-names = "timer";
416 timer1: timer1@ffc03100 {
417 compatible = "snps,dw-apb-timer";
418 interrupts = <0 114 4>;
419 reg = <0xffc03100 0x100>;
420 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
421 clock-names = "timer";
424 timer2: timer2@ffd00000 {
425 compatible = "snps,dw-apb-timer";
426 interrupts = <0 115 4>;
427 reg = <0xffd00000 0x100>;
428 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
429 clock-names = "timer";
432 timer3: timer3@ffd00100 {
433 compatible = "snps,dw-apb-timer";
434 interrupts = <0 116 4>;
435 reg = <0xffd00100 0x100>;
436 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
437 clock-names = "timer";
440 uart0: serial0@ffc02000 {
441 compatible = "snps,dw-apb-uart";
442 reg = <0xffc02000 0x100>;
443 interrupts = <0 108 4>;
446 resets = <&rst UART0_RESET>;
448 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
449 clock-frequency = <100000000>;
452 uart1: serial1@ffc02100 {
453 compatible = "snps,dw-apb-uart";
454 reg = <0xffc02100 0x100>;
455 interrupts = <0 109 4>;
458 resets = <&rst UART1_RESET>;
459 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
465 compatible = "usb-nop-xceiv";
470 compatible = "snps,dwc2";
471 reg = <0xffb00000 0x40000>;
472 interrupts = <0 93 4>;
474 phy-names = "usb2-phy";
475 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
476 reset-names = "dwc2", "dwc2-ecc";
477 clocks = <&clkmgr AGILEX_USB_CLK>;
483 compatible = "snps,dwc2";
484 reg = <0xffb40000 0x40000>;
485 interrupts = <0 94 4>;
487 phy-names = "usb2-phy";
488 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
489 reset-names = "dwc2", "dwc2-ecc";
491 clocks = <&clkmgr AGILEX_USB_CLK>;
495 watchdog0: watchdog@ffd00200 {
496 compatible = "snps,dw-wdt";
497 reg = <0xffd00200 0x100>;
498 interrupts = <0 117 4>;
499 resets = <&rst WATCHDOG0_RESET>;
500 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
504 watchdog1: watchdog@ffd00300 {
505 compatible = "snps,dw-wdt";
506 reg = <0xffd00300 0x100>;
507 interrupts = <0 118 4>;
508 resets = <&rst WATCHDOG1_RESET>;
509 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
513 watchdog2: watchdog@ffd00400 {
514 compatible = "snps,dw-wdt";
515 reg = <0xffd00400 0x100>;
516 interrupts = <0 125 4>;
517 resets = <&rst WATCHDOG2_RESET>;
518 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
522 watchdog3: watchdog@ffd00500 {
523 compatible = "snps,dw-wdt";
524 reg = <0xffd00500 0x100>;
525 interrupts = <0 126 4>;
526 resets = <&rst WATCHDOG3_RESET>;
527 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
532 compatible = "altr,sdr-ctl", "syscon";
533 reg = <0xf8011100 0xc0>;
537 compatible = "altr,socfpga-s10-ecc-manager",
538 "altr,socfpga-a10-ecc-manager";
539 altr,sysmgr-syscon = <&sysmgr>;
540 #address-cells = <1>;
542 interrupts = <0 15 4>;
543 interrupt-controller;
544 #interrupt-cells = <2>;
548 compatible = "altr,sdram-edac-s10";
549 altr,sdr-syscon = <&sdr>;
554 compatible = "altr,socfpga-s10-ocram-ecc",
555 "altr,socfpga-a10-ocram-ecc";
556 reg = <0xff8cc000 0x100>;
557 altr,ecc-parent = <&ocram>;
562 compatible = "altr,socfpga-s10-usb-ecc",
563 "altr,socfpga-usb-ecc";
564 reg = <0xff8c4000 0x100>;
565 altr,ecc-parent = <&usb0>;
569 emac0-rx-ecc@ff8c0000 {
570 compatible = "altr,socfpga-s10-eth-mac-ecc",
571 "altr,socfpga-eth-mac-ecc";
572 reg = <0xff8c0000 0x100>;
573 altr,ecc-parent = <&gmac0>;
577 emac0-tx-ecc@ff8c0400 {
578 compatible = "altr,socfpga-s10-eth-mac-ecc",
579 "altr,socfpga-eth-mac-ecc";
580 reg = <0xff8c0400 0x100>;
581 altr,ecc-parent = <&gmac0>;
585 sdmmca-ecc@ff8c8c00 {
586 compatible = "altr,socfpga-s10-sdmmc-ecc",
587 "altr,socfpga-sdmmc-ecc";
588 reg = <0xff8c8c00 0x100>;
589 altr,ecc-parent = <&mmc>;
596 compatible = "cdns,qspi-nor";
597 #address-cells = <1>;
599 reg = <0xff8d2000 0x100>,
600 <0xff900000 0x100000>;
601 interrupts = <0 3 4>;
602 cdns,fifo-depth = <128>;
603 cdns,fifo-width = <4>;
604 cdns,trigger-address = <0x00000000>;
605 clocks = <&qspi_clk>;
612 compatible = "intel,stratix10-svc";
614 memory-region = <&service_reserved>;
617 compatible = "intel,stratix10-soc-fpga-mgr";