2 * Copyright (C) 2012 Altera <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
7 #include "skeleton.dtsi"
8 #include <dt-bindings/reset/altr,rst-mgr.h>
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
47 reg = <0xfffed000 0x1000>,
54 compatible = "simple-bus";
56 interrupt-parent = <&intc>;
60 compatible = "arm,amba-bus";
66 compatible = "arm,pl330", "arm,primecell";
67 reg = <0xffe01000 0x1000>;
68 interrupts = <0 104 4>,
79 clocks = <&l4_main_clk>;
80 clock-names = "apb_pclk";
85 compatible = "bosch,d_can";
86 reg = <0xffc00000 0x1000>;
87 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
93 compatible = "bosch,d_can";
94 reg = <0xffc01000 0x1000>;
95 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
101 compatible = "altr,clk-mgr";
102 reg = <0xffd04000 0x1000>;
105 #address-cells = <1>;
110 compatible = "fixed-clock";
115 compatible = "fixed-clock";
118 f2s_periph_ref_clk: f2s_periph_ref_clk {
120 compatible = "fixed-clock";
123 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
125 compatible = "fixed-clock";
129 #address-cells = <1>;
132 compatible = "altr,socfpga-pll-clock";
138 compatible = "altr,socfpga-perip-clk";
139 clocks = <&main_pll>;
140 div-reg = <0xe0 0 9>;
146 compatible = "altr,socfpga-perip-clk";
147 clocks = <&main_pll>;
148 div-reg = <0xe4 0 9>;
152 dbg_base_clk: dbg_base_clk {
154 compatible = "altr,socfpga-perip-clk";
155 clocks = <&main_pll>;
156 div-reg = <0xe8 0 9>;
160 main_qspi_clk: main_qspi_clk {
162 compatible = "altr,socfpga-perip-clk";
163 clocks = <&main_pll>;
167 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
169 compatible = "altr,socfpga-perip-clk";
170 clocks = <&main_pll>;
174 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
176 compatible = "altr,socfpga-perip-clk";
177 clocks = <&main_pll>;
182 periph_pll: periph_pll {
183 #address-cells = <1>;
186 compatible = "altr,socfpga-pll-clock";
187 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
190 emac0_clk: emac0_clk {
192 compatible = "altr,socfpga-perip-clk";
193 clocks = <&periph_pll>;
197 emac1_clk: emac1_clk {
199 compatible = "altr,socfpga-perip-clk";
200 clocks = <&periph_pll>;
204 per_qspi_clk: per_qsi_clk {
206 compatible = "altr,socfpga-perip-clk";
207 clocks = <&periph_pll>;
211 per_nand_mmc_clk: per_nand_mmc_clk {
213 compatible = "altr,socfpga-perip-clk";
214 clocks = <&periph_pll>;
218 per_base_clk: per_base_clk {
220 compatible = "altr,socfpga-perip-clk";
221 clocks = <&periph_pll>;
225 h2f_usr1_clk: h2f_usr1_clk {
227 compatible = "altr,socfpga-perip-clk";
228 clocks = <&periph_pll>;
233 sdram_pll: sdram_pll {
234 #address-cells = <1>;
237 compatible = "altr,socfpga-pll-clock";
238 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
241 ddr_dqs_clk: ddr_dqs_clk {
243 compatible = "altr,socfpga-perip-clk";
244 clocks = <&sdram_pll>;
248 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
250 compatible = "altr,socfpga-perip-clk";
251 clocks = <&sdram_pll>;
255 ddr_dq_clk: ddr_dq_clk {
257 compatible = "altr,socfpga-perip-clk";
258 clocks = <&sdram_pll>;
262 h2f_usr2_clk: h2f_usr2_clk {
264 compatible = "altr,socfpga-perip-clk";
265 clocks = <&sdram_pll>;
270 mpu_periph_clk: mpu_periph_clk {
272 compatible = "altr,socfpga-perip-clk";
277 mpu_l2_ram_clk: mpu_l2_ram_clk {
279 compatible = "altr,socfpga-perip-clk";
284 l4_main_clk: l4_main_clk {
286 compatible = "altr,socfpga-gate-clk";
291 l3_main_clk: l3_main_clk {
293 compatible = "altr,socfpga-perip-clk";
298 l3_mp_clk: l3_mp_clk {
300 compatible = "altr,socfpga-gate-clk";
302 div-reg = <0x64 0 2>;
306 l3_sp_clk: l3_sp_clk {
308 compatible = "altr,socfpga-gate-clk";
310 div-reg = <0x64 2 2>;
313 l4_mp_clk: l4_mp_clk {
315 compatible = "altr,socfpga-gate-clk";
316 clocks = <&mainclk>, <&per_base_clk>;
317 div-reg = <0x64 4 3>;
321 l4_sp_clk: l4_sp_clk {
323 compatible = "altr,socfpga-gate-clk";
324 clocks = <&mainclk>, <&per_base_clk>;
325 div-reg = <0x64 7 3>;
329 dbg_at_clk: dbg_at_clk {
331 compatible = "altr,socfpga-gate-clk";
332 clocks = <&dbg_base_clk>;
333 div-reg = <0x68 0 2>;
339 compatible = "altr,socfpga-gate-clk";
340 clocks = <&dbg_base_clk>;
341 div-reg = <0x68 2 2>;
345 dbg_trace_clk: dbg_trace_clk {
347 compatible = "altr,socfpga-gate-clk";
348 clocks = <&dbg_base_clk>;
349 div-reg = <0x6C 0 3>;
353 dbg_timer_clk: dbg_timer_clk {
355 compatible = "altr,socfpga-gate-clk";
356 clocks = <&dbg_base_clk>;
362 compatible = "altr,socfpga-gate-clk";
363 clocks = <&cfg_h2f_usr0_clk>;
367 h2f_user0_clk: h2f_user0_clk {
369 compatible = "altr,socfpga-gate-clk";
370 clocks = <&cfg_h2f_usr0_clk>;
374 emac_0_clk: emac_0_clk {
376 compatible = "altr,socfpga-gate-clk";
377 clocks = <&emac0_clk>;
381 emac_1_clk: emac_1_clk {
383 compatible = "altr,socfpga-gate-clk";
384 clocks = <&emac1_clk>;
388 usb_mp_clk: usb_mp_clk {
390 compatible = "altr,socfpga-gate-clk";
391 clocks = <&per_base_clk>;
393 div-reg = <0xa4 0 3>;
396 spi_m_clk: spi_m_clk {
398 compatible = "altr,socfpga-gate-clk";
399 clocks = <&per_base_clk>;
401 div-reg = <0xa4 3 3>;
406 compatible = "altr,socfpga-gate-clk";
407 clocks = <&per_base_clk>;
409 div-reg = <0xa4 6 3>;
414 compatible = "altr,socfpga-gate-clk";
415 clocks = <&per_base_clk>;
417 div-reg = <0xa4 9 3>;
420 gpio_db_clk: gpio_db_clk {
422 compatible = "altr,socfpga-gate-clk";
423 clocks = <&per_base_clk>;
425 div-reg = <0xa8 0 24>;
428 h2f_user1_clk: h2f_user1_clk {
430 compatible = "altr,socfpga-gate-clk";
431 clocks = <&h2f_usr1_clk>;
435 sdmmc_clk: sdmmc_clk {
437 compatible = "altr,socfpga-gate-clk";
438 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
443 nand_x_clk: nand_x_clk {
445 compatible = "altr,socfpga-gate-clk";
446 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
452 compatible = "altr,socfpga-gate-clk";
453 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
454 clk-gate = <0xa0 10>;
460 compatible = "altr,socfpga-gate-clk";
461 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
462 clk-gate = <0xa0 11>;
467 gmac0: ethernet@ff700000 {
468 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
469 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
470 reg = <0xff700000 0x2000>;
471 interrupts = <0 115 4>;
472 interrupt-names = "macirq";
473 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
474 clocks = <&emac0_clk>;
475 clock-names = "stmmaceth";
476 resets = <&rst EMAC0_RESET>;
477 reset-names = "stmmaceth";
478 snps,multicast-filter-bins = <256>;
479 snps,perfect-filter-entries = <128>;
483 gmac1: ethernet@ff702000 {
484 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
485 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
486 reg = <0xff702000 0x2000>;
487 interrupts = <0 120 4>;
488 interrupt-names = "macirq";
489 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
490 clocks = <&emac1_clk>;
491 clock-names = "stmmaceth";
492 resets = <&rst EMAC1_RESET>;
493 reset-names = "stmmaceth";
494 snps,multicast-filter-bins = <256>;
495 snps,perfect-filter-entries = <128>;
500 #address-cells = <1>;
502 compatible = "snps,designware-i2c";
503 reg = <0xffc04000 0x1000>;
504 clocks = <&l4_sp_clk>;
505 interrupts = <0 158 0x4>;
510 #address-cells = <1>;
512 compatible = "snps,designware-i2c";
513 reg = <0xffc05000 0x1000>;
514 clocks = <&l4_sp_clk>;
515 interrupts = <0 159 0x4>;
520 #address-cells = <1>;
522 compatible = "snps,designware-i2c";
523 reg = <0xffc06000 0x1000>;
524 clocks = <&l4_sp_clk>;
525 interrupts = <0 160 0x4>;
530 #address-cells = <1>;
532 compatible = "snps,designware-i2c";
533 reg = <0xffc07000 0x1000>;
534 clocks = <&l4_sp_clk>;
535 interrupts = <0 161 0x4>;
539 gpio0: gpio@ff708000 {
540 #address-cells = <1>;
542 compatible = "snps,dw-apb-gpio";
543 reg = <0xff708000 0x1000>;
544 clocks = <&per_base_clk>;
547 porta: gpio-controller@0 {
548 compatible = "snps,dw-apb-gpio-port";
551 snps,nr-gpios = <29>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 interrupts = <0 164 4>;
559 gpio1: gpio@ff709000 {
560 #address-cells = <1>;
562 compatible = "snps,dw-apb-gpio";
563 reg = <0xff709000 0x1000>;
564 clocks = <&per_base_clk>;
567 portb: gpio-controller@0 {
568 compatible = "snps,dw-apb-gpio-port";
571 snps,nr-gpios = <29>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 interrupts = <0 165 4>;
579 gpio2: gpio@ff70a000 {
580 #address-cells = <1>;
582 compatible = "snps,dw-apb-gpio";
583 reg = <0xff70a000 0x1000>;
584 clocks = <&per_base_clk>;
587 portc: gpio-controller@0 {
588 compatible = "snps,dw-apb-gpio-port";
591 snps,nr-gpios = <27>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 interrupts = <0 166 4>;
600 compatible = "syscon";
601 reg = <0xffc25000 0x1000>;
605 compatible = "altr,sdram-edac";
606 altr,sdr-syscon = <&sdr>;
607 interrupts = <0 39 4>;
610 L2: l2-cache@fffef000 {
611 compatible = "arm,pl310-cache";
612 reg = <0xfffef000 0x1000>;
613 interrupts = <0 38 0x04>;
616 arm,tag-latency = <1 1 1>;
617 arm,data-latency = <2 1 1>;
620 mmc: dwmmc0@ff704000 {
621 compatible = "altr,socfpga-dw-mshc";
622 reg = <0xff704000 0x1000>;
623 interrupts = <0 139 4>;
624 fifo-depth = <0x400>;
625 #address-cells = <1>;
627 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
628 clock-names = "biu", "ciu";
632 compatible = "cadence,qspi";
633 #address-cells = <1>;
635 reg = <0xff705000 0x1000>,
637 interrupts = <0 151 4>;
638 clocks = <&qspi_clk>;
639 ext-decoder = <0>; /* external decoder */
647 compatible = "snps,dw-apb-ssi";
648 #address-cells = <1>;
650 reg = <0xfff00000 0x1000>;
651 interrupts = <0 154 4>;
654 tx-dma-channel = <&pdma 16>;
655 rx-dma-channel = <&pdma 17>;
656 clocks = <&per_base_clk>;
661 compatible = "snps,dw-apb-ssi";
662 #address-cells = <1>;
664 reg = <0xfff01000 0x1000>;
665 interrupts = <0 156 4>;
668 tx-dma-channel = <&pdma 20>;
669 rx-dma-channel = <&pdma 21>;
670 clocks = <&per_base_clk>;
676 compatible = "arm,cortex-a9-twd-timer";
677 reg = <0xfffec600 0x100>;
678 interrupts = <1 13 0xf04>;
679 clocks = <&mpu_periph_clk>;
682 timer0: timer0@ffc08000 {
683 compatible = "snps,dw-apb-timer";
684 interrupts = <0 167 4>;
685 reg = <0xffc08000 0x1000>;
686 clocks = <&l4_sp_clk>;
687 clock-names = "timer";
690 timer1: timer1@ffc09000 {
691 compatible = "snps,dw-apb-timer";
692 interrupts = <0 168 4>;
693 reg = <0xffc09000 0x1000>;
694 clocks = <&l4_sp_clk>;
695 clock-names = "timer";
698 timer2: timer2@ffd00000 {
699 compatible = "snps,dw-apb-timer";
700 interrupts = <0 169 4>;
701 reg = <0xffd00000 0x1000>;
703 clock-names = "timer";
706 timer3: timer3@ffd01000 {
707 compatible = "snps,dw-apb-timer";
708 interrupts = <0 170 4>;
709 reg = <0xffd01000 0x1000>;
711 clock-names = "timer";
714 uart0: serial0@ffc02000 {
715 compatible = "snps,dw-apb-uart";
716 reg = <0xffc02000 0x1000>;
717 interrupts = <0 162 4>;
720 clocks = <&l4_sp_clk>;
723 uart1: serial1@ffc03000 {
724 compatible = "snps,dw-apb-uart";
725 reg = <0xffc03000 0x1000>;
726 interrupts = <0 163 4>;
729 clocks = <&l4_sp_clk>;
732 rst: rstmgr@ffd05000 {
734 compatible = "altr,rst-mgr";
735 reg = <0xffd05000 0x1000>;
740 compatible = "usb-nop-xceiv";
745 compatible = "snps,dwc2";
746 reg = <0xffb00000 0xffff>;
747 interrupts = <0 125 4>;
748 clocks = <&usb_mp_clk>;
751 phy-names = "usb2-phy";
756 compatible = "snps,dwc2";
757 reg = <0xffb40000 0xffff>;
758 interrupts = <0 128 4>;
759 clocks = <&usb_mp_clk>;
762 phy-names = "usb2-phy";
766 watchdog0: watchdog@ffd02000 {
767 compatible = "snps,dw-wdt";
768 reg = <0xffd02000 0x1000>;
769 interrupts = <0 171 4>;
774 watchdog1: watchdog@ffd03000 {
775 compatible = "snps,dw-wdt";
776 reg = <0xffd03000 0x1000>;
777 interrupts = <0 172 4>;
782 sysmgr: sysmgr@ffd08000 {
783 compatible = "altr,sys-mgr", "syscon";
784 reg = <0xffd08000 0x4000>;