1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera <www.altera.com>
6 #include "skeleton.dtsi"
7 #include <dt-bindings/reset/altr,rst-mgr.h>
36 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a9";
45 next-level-cache = <&L2>;
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
53 reg = <0xfffed000 0x1000>,
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "arm,amba-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
85 clocks = <&l4_main_clk>;
86 clock-names = "apb_pclk";
91 compatible = "bosch,d_can";
92 reg = <0xffc00000 0x1000>;
93 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
99 compatible = "bosch,d_can";
100 reg = <0xffc01000 0x1000>;
101 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
102 clocks = <&can1_clk>;
107 compatible = "altr,clk-mgr";
108 reg = <0xffd04000 0x1000>;
111 #address-cells = <1>;
116 compatible = "fixed-clock";
121 compatible = "fixed-clock";
124 f2s_periph_ref_clk: f2s_periph_ref_clk {
126 compatible = "fixed-clock";
129 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
131 compatible = "fixed-clock";
135 #address-cells = <1>;
138 compatible = "altr,socfpga-pll-clock";
144 compatible = "altr,socfpga-perip-clk";
145 clocks = <&main_pll>;
146 div-reg = <0xe0 0 9>;
152 compatible = "altr,socfpga-perip-clk";
153 clocks = <&main_pll>;
154 div-reg = <0xe4 0 9>;
158 dbg_base_clk: dbg_base_clk {
160 compatible = "altr,socfpga-perip-clk";
161 clocks = <&main_pll>;
162 div-reg = <0xe8 0 9>;
166 main_qspi_clk: main_qspi_clk {
168 compatible = "altr,socfpga-perip-clk";
169 clocks = <&main_pll>;
173 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
175 compatible = "altr,socfpga-perip-clk";
176 clocks = <&main_pll>;
180 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&main_pll>;
188 periph_pll: periph_pll {
189 #address-cells = <1>;
192 compatible = "altr,socfpga-pll-clock";
193 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
196 emac0_clk: emac0_clk {
198 compatible = "altr,socfpga-perip-clk";
199 clocks = <&periph_pll>;
203 emac1_clk: emac1_clk {
205 compatible = "altr,socfpga-perip-clk";
206 clocks = <&periph_pll>;
210 per_qspi_clk: per_qsi_clk {
212 compatible = "altr,socfpga-perip-clk";
213 clocks = <&periph_pll>;
217 per_nand_mmc_clk: per_nand_mmc_clk {
219 compatible = "altr,socfpga-perip-clk";
220 clocks = <&periph_pll>;
224 per_base_clk: per_base_clk {
226 compatible = "altr,socfpga-perip-clk";
227 clocks = <&periph_pll>;
231 h2f_usr1_clk: h2f_usr1_clk {
233 compatible = "altr,socfpga-perip-clk";
234 clocks = <&periph_pll>;
239 sdram_pll: sdram_pll {
240 #address-cells = <1>;
243 compatible = "altr,socfpga-pll-clock";
244 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
247 ddr_dqs_clk: ddr_dqs_clk {
249 compatible = "altr,socfpga-perip-clk";
250 clocks = <&sdram_pll>;
254 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
256 compatible = "altr,socfpga-perip-clk";
257 clocks = <&sdram_pll>;
261 ddr_dq_clk: ddr_dq_clk {
263 compatible = "altr,socfpga-perip-clk";
264 clocks = <&sdram_pll>;
268 h2f_usr2_clk: h2f_usr2_clk {
270 compatible = "altr,socfpga-perip-clk";
271 clocks = <&sdram_pll>;
276 mpu_periph_clk: mpu_periph_clk {
278 compatible = "altr,socfpga-perip-clk";
283 mpu_l2_ram_clk: mpu_l2_ram_clk {
285 compatible = "altr,socfpga-perip-clk";
290 l4_main_clk: l4_main_clk {
292 compatible = "altr,socfpga-gate-clk";
297 l3_main_clk: l3_main_clk {
299 compatible = "altr,socfpga-perip-clk";
304 l3_mp_clk: l3_mp_clk {
306 compatible = "altr,socfpga-gate-clk";
308 div-reg = <0x64 0 2>;
312 l3_sp_clk: l3_sp_clk {
314 compatible = "altr,socfpga-gate-clk";
316 div-reg = <0x64 2 2>;
319 l4_mp_clk: l4_mp_clk {
321 compatible = "altr,socfpga-gate-clk";
322 clocks = <&mainclk>, <&per_base_clk>;
323 div-reg = <0x64 4 3>;
327 l4_sp_clk: l4_sp_clk {
329 compatible = "altr,socfpga-gate-clk";
330 clocks = <&mainclk>, <&per_base_clk>;
331 div-reg = <0x64 7 3>;
335 dbg_at_clk: dbg_at_clk {
337 compatible = "altr,socfpga-gate-clk";
338 clocks = <&dbg_base_clk>;
339 div-reg = <0x68 0 2>;
345 compatible = "altr,socfpga-gate-clk";
346 clocks = <&dbg_base_clk>;
347 div-reg = <0x68 2 2>;
351 dbg_trace_clk: dbg_trace_clk {
353 compatible = "altr,socfpga-gate-clk";
354 clocks = <&dbg_base_clk>;
355 div-reg = <0x6C 0 3>;
359 dbg_timer_clk: dbg_timer_clk {
361 compatible = "altr,socfpga-gate-clk";
362 clocks = <&dbg_base_clk>;
368 compatible = "altr,socfpga-gate-clk";
369 clocks = <&cfg_h2f_usr0_clk>;
373 h2f_user0_clk: h2f_user0_clk {
375 compatible = "altr,socfpga-gate-clk";
376 clocks = <&cfg_h2f_usr0_clk>;
380 emac_0_clk: emac_0_clk {
382 compatible = "altr,socfpga-gate-clk";
383 clocks = <&emac0_clk>;
387 emac_1_clk: emac_1_clk {
389 compatible = "altr,socfpga-gate-clk";
390 clocks = <&emac1_clk>;
394 usb_mp_clk: usb_mp_clk {
396 compatible = "altr,socfpga-gate-clk";
397 clocks = <&per_base_clk>;
399 div-reg = <0xa4 0 3>;
402 spi_m_clk: spi_m_clk {
404 compatible = "altr,socfpga-gate-clk";
405 clocks = <&per_base_clk>;
407 div-reg = <0xa4 3 3>;
412 compatible = "altr,socfpga-gate-clk";
413 clocks = <&per_base_clk>;
415 div-reg = <0xa4 6 3>;
420 compatible = "altr,socfpga-gate-clk";
421 clocks = <&per_base_clk>;
423 div-reg = <0xa4 9 3>;
426 gpio_db_clk: gpio_db_clk {
428 compatible = "altr,socfpga-gate-clk";
429 clocks = <&per_base_clk>;
431 div-reg = <0xa8 0 24>;
434 h2f_user1_clk: h2f_user1_clk {
436 compatible = "altr,socfpga-gate-clk";
437 clocks = <&h2f_usr1_clk>;
441 sdmmc_clk: sdmmc_clk {
443 compatible = "altr,socfpga-gate-clk";
444 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
449 nand_x_clk: nand_x_clk {
451 compatible = "altr,socfpga-gate-clk";
452 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
458 compatible = "altr,socfpga-gate-clk";
459 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
460 clk-gate = <0xa0 10>;
466 compatible = "altr,socfpga-gate-clk";
467 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
468 clk-gate = <0xa0 11>;
473 gmac0: ethernet@ff700000 {
474 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
475 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
476 reg = <0xff700000 0x2000>;
477 interrupts = <0 115 4>;
478 interrupt-names = "macirq";
479 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
480 clocks = <&emac0_clk>;
481 clock-names = "stmmaceth";
482 resets = <&rst EMAC0_RESET>;
483 reset-names = "stmmaceth";
484 snps,multicast-filter-bins = <256>;
485 snps,perfect-filter-entries = <128>;
489 gmac1: ethernet@ff702000 {
490 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
491 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
492 reg = <0xff702000 0x2000>;
493 interrupts = <0 120 4>;
494 interrupt-names = "macirq";
495 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
496 clocks = <&emac1_clk>;
497 clock-names = "stmmaceth";
498 resets = <&rst EMAC1_RESET>;
499 reset-names = "stmmaceth";
500 snps,multicast-filter-bins = <256>;
501 snps,perfect-filter-entries = <128>;
506 #address-cells = <1>;
508 compatible = "snps,designware-i2c";
509 reg = <0xffc04000 0x1000>;
510 clocks = <&l4_sp_clk>;
511 resets = <&rst I2C0_RESET>;
513 interrupts = <0 158 0x4>;
518 #address-cells = <1>;
520 compatible = "snps,designware-i2c";
521 reg = <0xffc05000 0x1000>;
522 clocks = <&l4_sp_clk>;
523 resets = <&rst I2C1_RESET>;
525 interrupts = <0 159 0x4>;
530 #address-cells = <1>;
532 compatible = "snps,designware-i2c";
533 reg = <0xffc06000 0x1000>;
534 clocks = <&l4_sp_clk>;
535 resets = <&rst I2C2_RESET>;
537 interrupts = <0 160 0x4>;
542 #address-cells = <1>;
544 compatible = "snps,designware-i2c";
545 reg = <0xffc07000 0x1000>;
546 clocks = <&l4_sp_clk>;
547 resets = <&rst I2C3_RESET>;
549 interrupts = <0 161 0x4>;
553 gpio0: gpio@ff708000 {
554 #address-cells = <1>;
556 compatible = "snps,dw-apb-gpio";
557 reg = <0xff708000 0x1000>;
558 clocks = <&per_base_clk>;
561 porta: gpio-controller@0 {
562 compatible = "snps,dw-apb-gpio-port";
566 snps,nr-gpios = <29>;
568 interrupt-controller;
569 #interrupt-cells = <2>;
570 interrupts = <0 164 4>;
574 gpio1: gpio@ff709000 {
575 #address-cells = <1>;
577 compatible = "snps,dw-apb-gpio";
578 reg = <0xff709000 0x1000>;
579 clocks = <&per_base_clk>;
582 portb: gpio-controller@0 {
583 compatible = "snps,dw-apb-gpio-port";
587 snps,nr-gpios = <29>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
591 interrupts = <0 165 4>;
595 gpio2: gpio@ff70a000 {
596 #address-cells = <1>;
598 compatible = "snps,dw-apb-gpio";
599 reg = <0xff70a000 0x1000>;
600 clocks = <&per_base_clk>;
603 portc: gpio-controller@0 {
604 compatible = "snps,dw-apb-gpio-port";
608 snps,nr-gpios = <27>;
610 interrupt-controller;
611 #interrupt-cells = <2>;
612 interrupts = <0 166 4>;
617 compatible = "syscon";
618 reg = <0xffc25000 0x1000>;
622 compatible = "altr,sdram-edac";
623 altr,sdr-syscon = <&sdr>;
624 interrupts = <0 39 4>;
627 L2: l2-cache@fffef000 {
628 compatible = "arm,pl310-cache";
629 reg = <0xfffef000 0x1000>;
630 interrupts = <0 38 0x04>;
633 arm,tag-latency = <1 1 1>;
634 arm,data-latency = <2 1 1>;
637 mmc0: dwmmc0@ff704000 {
638 compatible = "altr,socfpga-dw-mshc";
639 reg = <0xff704000 0x1000>;
640 interrupts = <0 139 4>;
641 fifo-depth = <0x400>;
642 #address-cells = <1>;
644 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
645 clock-names = "biu", "ciu";
649 compatible = "cadence,qspi";
650 #address-cells = <1>;
652 reg = <0xff705000 0x1000>,
654 interrupts = <0 151 4>;
655 clocks = <&qspi_clk>;
656 ext-decoder = <0>; /* external decoder */
658 cdns,fifo-depth = <128>;
659 cdns,fifo-width = <4>;
660 cdns,trigger-address = <0x00000000>;
666 compatible = "snps,dw-apb-ssi";
667 #address-cells = <1>;
669 reg = <0xfff00000 0x1000>;
670 interrupts = <0 154 4>;
673 tx-dma-channel = <&pdma 16>;
674 rx-dma-channel = <&pdma 17>;
675 clocks = <&per_base_clk>;
680 compatible = "snps,dw-apb-ssi";
681 #address-cells = <1>;
683 reg = <0xfff01000 0x1000>;
684 interrupts = <0 156 4>;
687 tx-dma-channel = <&pdma 20>;
688 rx-dma-channel = <&pdma 21>;
689 clocks = <&per_base_clk>;
695 compatible = "arm,cortex-a9-twd-timer";
696 reg = <0xfffec600 0x100>;
697 interrupts = <1 13 0xf04>;
698 clocks = <&mpu_periph_clk>;
701 timer0: timer0@ffc08000 {
702 compatible = "snps,dw-apb-timer";
703 interrupts = <0 167 4>;
704 reg = <0xffc08000 0x1000>;
705 clocks = <&l4_sp_clk>;
706 clock-names = "timer";
709 timer1: timer1@ffc09000 {
710 compatible = "snps,dw-apb-timer";
711 interrupts = <0 168 4>;
712 reg = <0xffc09000 0x1000>;
713 clocks = <&l4_sp_clk>;
714 clock-names = "timer";
717 timer2: timer2@ffd00000 {
718 compatible = "snps,dw-apb-timer";
719 interrupts = <0 169 4>;
720 reg = <0xffd00000 0x1000>;
722 clock-names = "timer";
725 timer3: timer3@ffd01000 {
726 compatible = "snps,dw-apb-timer";
727 interrupts = <0 170 4>;
728 reg = <0xffd01000 0x1000>;
730 clock-names = "timer";
733 uart0: serial0@ffc02000 {
734 compatible = "snps,dw-apb-uart";
735 reg = <0xffc02000 0x1000>;
736 interrupts = <0 162 4>;
739 clocks = <&l4_sp_clk>;
740 clock-frequency = <100000000>;
743 uart1: serial1@ffc03000 {
744 compatible = "snps,dw-apb-uart";
745 reg = <0xffc03000 0x1000>;
746 interrupts = <0 163 4>;
749 clocks = <&l4_sp_clk>;
750 clock-frequency = <100000000>;
753 rst: rstmgr@ffd05000 {
755 compatible = "altr,rst-mgr";
756 reg = <0xffd05000 0x1000>;
761 compatible = "usb-nop-xceiv";
766 compatible = "snps,dwc2";
767 reg = <0xffb00000 0xffff>;
768 interrupts = <0 125 4>;
769 clocks = <&usb_mp_clk>;
772 phy-names = "usb2-phy";
777 compatible = "snps,dwc2";
778 reg = <0xffb40000 0xffff>;
779 interrupts = <0 128 4>;
780 clocks = <&usb_mp_clk>;
783 phy-names = "usb2-phy";
787 watchdog0: watchdog@ffd02000 {
788 compatible = "snps,dw-wdt";
789 reg = <0xffd02000 0x1000>;
790 interrupts = <0 171 4>;
795 watchdog1: watchdog@ffd03000 {
796 compatible = "snps,dw-wdt";
797 reg = <0xffd03000 0x1000>;
798 interrupts = <0 172 4>;
803 sysmgr: sysmgr@ffd08000 {
804 compatible = "altr,sys-mgr", "syscon";
805 reg = <0xffd08000 0x4000>;